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// -*- mode:c++ -*-
// Copyright (c) 2007 MIPS Technologies, Inc.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Korey Sewell
// Jaidev Patwardhan
////////////////////////////////////////////////////////////////////
//
// Coprocessor instructions
//
//Outputs to decoder.hh
output header {{
class CP0Control : public MipsStaticInst
{
protected:
/// Constructor
CP0Control(const char *mnem, MachInst _machInst, OpClass __opClass) :
MipsStaticInst(mnem, _machInst, __opClass)
{
}
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
class CP0TLB : public MipsStaticInst
{
protected:
/// Constructor
CP0TLB(const char *mnem, MachInst _machInst, OpClass __opClass) :
MipsStaticInst(mnem, _machInst, __opClass)
{
}
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
class CP1Control : public MipsStaticInst
{
protected:
/// Constructor
CP1Control(const char *mnem, MachInst _machInst, OpClass __opClass) :
MipsStaticInst(mnem, _machInst, __opClass)
{
}
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
}};
// Basic instruction class execute method template.
def template CP0Execute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;
%(op_rd)s;
if (isCoprocessorEnabled(xc, 0)) {
%(code)s;
} else {
fault = new CoprocessorUnusableFault(0);
}
if(fault == NoFault)
{
%(op_wb)s;
}
return fault;
}
}};
def template CP1Execute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;
%(op_rd)s;
if (isCoprocessorEnabled(xc, 1)) {
%(code)s;
} else {
fault = new CoprocessorUnusableFault(1);
}
if(fault == NoFault)
{
%(op_wb)s;
}
return fault;
}
}};
// Basic instruction class execute method template.
def template ControlTLBExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;
%(op_rd)s;
#if FULL_SYSTEM
if (isCoprocessor0Enabled(xc)) {
if(isMMUTLB(xc)){
%(code)s;
} else {
fault = new ReservedInstructionFault();
}
} else {
fault = new CoprocessorUnusableFault(0);
}
#else // Syscall Emulation Mode - No TLB Instructions
fault = new ReservedInstructionFault();
#endif
if(fault == NoFault)
{
%(op_wb)s;
}
return fault;
}
}};
//Outputs to decoder.cc
output decoder {{
std::string CP0Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
ccprintf(ss, "%-10s r%d, %d, %d", mnemonic, RT, RD, SEL);
return ss.str();
}
std::string CP0TLB::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
ccprintf(ss, "%-10s r%d, %d, %d", mnemonic, RT, RD, SEL);
return ss.str();
}
std::string CP1Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
ccprintf(ss, "%-10s r%d, f%d", mnemonic, RT, FS);
return ss.str();
}
}};
output exec {{
bool isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num)
{
#if !FULL_SYSTEM
return true;
#else
MiscReg Stat = xc->readMiscReg(MISCREG_STATUS);
switch(cop_num)
{
case 0:
{
MiscReg Dbg = xc->readMiscReg(MISCREG_DEBUG);
if((Stat & 0x10000006) == 0 // EXL, ERL or CU0 set, CP0 accessible
&& (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible
&& (Stat & 0x00000018) != 0) { // KSU = 0, kernel mode is base mode
// Unable to use Status_CU0, etc directly, using bitfields & masks
return false;
}
}
break;
case 1:
if((Stat & 0x20000000) == 0) // CU1 is reset
return false;
break;
case 2:
if((Stat & 0x40000000) == 0) // CU2 is reset
return false;
break;
case 3:
if((Stat & 0x80000000) == 0) // CU3 is reset
return false;
break;
default: panic("Invalid Coprocessor Number Specified");
break;
}
return true;
#endif
}
bool inline isCoprocessor0Enabled(%(CPU_exec_context)s *xc)
{
#if FULL_SYSTEM
MiscReg Stat = xc->readMiscRegNoEffect(MISCREG_STATUS);
MiscReg Dbg = xc->readMiscRegNoEffect(MISCREG_DEBUG);
if((Stat & 0x10000006) == 0 // EXL, ERL or CU0 set, CP0 accessible
&& (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible
&& (Stat & 0x00000018) != 0) { // KSU = 0, kernel mode is base mode
// Unable to use Status_CU0, etc directly, using bitfields & masks
return false;
}
#else
//printf("Syscall Emulation Mode: CP0 Enable Check defaults to TRUE\n");
#endif
return true;
}
bool isMMUTLB(%(CPU_exec_context)s *xc)
{
#if FULL_SYSTEM
if((xc->readMiscRegNoEffect(MISCREG_CONFIG) & 0x00000380)==0x80)
return true;
#endif
return false;
}
}};
def format CP0Control(code, *flags) {{
flags += ('IsNonSpeculative', )
iop = InstObjParams(name, Name, 'CP0Control', code, flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = CP0Execute.subst(iop)
}};
def format CP0TLB(code, *flags) {{
flags += ('IsNonSpeculative', )
iop = InstObjParams(name, Name, 'CP0Control', code, flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = ControlTLBExecute.subst(iop)
}};
def format CP1Control(code, *flags) {{
flags += ('IsNonSpeculative', )
iop = InstObjParams(name, Name, 'CP1Control', code, flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = CP1Execute.subst(iop)
}};
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