1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
|
// -*- mode:c++ -*-
// Copyright (c) 2003-2005 The Regents of The University of Michigan
// Copyright (c) 2009 The University of Edinburgh
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Steve Reinhardt
// Korey Sewell
// Timothy M. Jones
// Some instructions ignore the contents of Ra if Ra == 0,
// so check for this.
def template CheckRaDecode {{
{
if (RA == 0) {
return new %(class_name)sRaZero(machInst);
} else {
return new %(class_name)s(machInst);
}
}
}};
// Some instructions have extra behaviour if Rc is set.
def template CheckRcDecode {{
{
if (RC31 == 0) {
return new %(class_name)s(machInst);
} else {
return new %(class_name)sRcSet(machInst);
}
}
}};
// Some instructions have extra behaviour if Rc and OE are set.
def template CheckRcOeDecode {{
{
if (RC31 == 0) {
if (OE == 0) {
return new %(class_name)s(machInst);
} else {
return new %(class_name)sOeSet(machInst);
}
} else {
if (OE == 0) {
return new %(class_name)sRcSet(machInst);
} else {
return new %(class_name)sRcSetOeSet(machInst);
}
}
}
}};
// Branch instructions always have two versions, one which sets the link
// register (LR).
def template CheckLkDecode {{
{
if (LK == 0) {
return new %(class_name)s(machInst);
} else {
return new %(class_name)sUpdateLr(machInst);
}
}
}};
let {{
def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
base_class = 'MemOp',
decode_template = BasicDecode, exec_template_base = ''):
# Make sure flags are in lists (convert to lists if not).
mem_flags = makeList(mem_flags)
inst_flags = makeList(inst_flags)
# add hook to get effective addresses into execution trace output.
ea_code += '\nif (traceData) { traceData->setAddr(EA); }\n'
# Generate InstObjParams for the memory access.
iop = InstObjParams(name, Name, base_class,
{'ea_code': ea_code,
'memacc_code': memacc_code},
inst_flags)
if mem_flags:
s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';'
iop.constructor += s
fullExecTemplate = eval(exec_template_base + 'Execute')
initiateAccTemplate = eval(exec_template_base + 'InitiateAcc')
completeAccTemplate = eval(exec_template_base + 'CompleteAcc')
# (header_output, decoder_output, decode_block, exec_output)
return (LoadStoreDeclare.subst(iop),
LoadStoreConstructor.subst(iop),
decode_template.subst(iop),
fullExecTemplate.subst(iop)
+ initiateAccTemplate.subst(iop)
+ completeAccTemplate.subst(iop))
# The generic ALU instruction generator. Integer and fp formats calls this
# to generate the different output sections.
def GenAluOp(name, Name, base_class, code, inst_flags, decode_template,
constructor_template):
iop = InstObjParams(name, Name, base_class,
{"code": code},
inst_flags)
header_output = BasicDeclare.subst(iop)
exec_output = BasicExecute.subst(iop)
# We use constructors dependent on the Rc and OE bits being set
decoder_output = constructor_template.subst(iop)
# The decode block defines which version to use
decode_block = decode_template.subst(iop)
return (header_output, decoder_output, decode_block, exec_output)
}};
output header {{
std::string
inst2string(MachInst machInst);
}};
output decoder {{
std::string
inst2string(MachInst machInst)
{
std::string str = "";
uint32_t mask = 0x80000000;
for(int i=0; i < 32; i++) {
if ((machInst & mask) == 0) {
str += "0";
} else {
str += "1";
}
mask = mask >> 1;
}
return str;
}
}};
|