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// -*- mode:c++ -*-
// Copyright (c) 2015 RISC-V Foundation
// Copyright (c) 2017 The University of Virginia
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Alec Roelke
def format CROp(code, *opt_flags) {{
iop = InstObjParams(name, Name, 'CompRegOp', code, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = BasicExecute.subst(iop)
}};
def format CIAddi4spnOp(imm_code, code, imm_type='int64_t', *opt_flags) {{
regs = ['_destRegIdx[0]', '_srcRegIdx[0]']
iop = InstObjParams(name, Name, 'ImmOp<%s>' % imm_type,
{'code': code, 'imm_code': imm_code,
'regs': ','.join(regs)}, opt_flags)
header_output = ImmDeclare.subst(iop)
decoder_output = ImmConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = ImmExecute.subst(iop)
}};
def format CIOp(imm_code, code, imm_type='int64_t', *opt_flags) {{
iop = InstObjParams(name, Name, 'ImmOp<%s>' % imm_type,
{'code': code, 'imm_code': imm_code,
'regs': '_destRegIdx[0]'}, opt_flags)
header_output = ImmDeclare.subst(iop)
decoder_output = ImmConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
if (name == "c_lui"):
exec_output = CILuiExecute.subst(iop)
else:
exec_output = ImmExecute.subst(iop)
}};
def format CJOp(code, *opt_flags) {{
imm_code = """
imm = CJUMPIMM3TO1 << 1 |
CJUMPIMM4TO4 << 4 |
CJUMPIMM5TO5 << 5 |
CJUMPIMM6TO6 << 6 |
CJUMPIMM7TO7 << 7 |
CJUMPIMM9TO8 << 8 |
CJUMPIMM10TO10 << 10;
if (CJUMPIMMSIGN)
imm |= ~((int64_t)0x7FF);
"""
iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
{'code': code, 'imm_code': imm_code,
'regs': ''}, opt_flags)
header_output = BranchDeclare.subst(iop)
decoder_output = ImmConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = BranchExecute.subst(iop)
}};
def format CBOp(code, *opt_flags) {{
imm_code = """
imm = CIMM5<2:1> << 1 |
CIMM3<1:0> << 3 |
CIMM5<0:0> << 5 |
CIMM5<4:3> << 6;
if (CIMM3<2:2> > 0)
imm |= ~((int64_t)0xFF);
"""
regs = '_srcRegIdx[0]'
iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
{'code': code, 'imm_code': imm_code,
'regs': '_srcRegIdx[0]'}, opt_flags)
header_output = BranchDeclare.subst(iop)
decoder_output = ImmConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = BranchExecute.subst(iop)
}};
def format CompressedLoad(ldisp_code, memacc_code,
ea_code, mem_flags=[], inst_flags=[]) {{
(header_output, decoder_output, decode_block, exec_output) = \
LoadStoreBase(name, Name, ldisp_code, ea_code, memacc_code, mem_flags,
inst_flags, 'Load', exec_template_base='Load')
}};
def format CompressedStore(sdisp_code, memacc_code,
ea_code, mem_flags=[], inst_flags=[]) {{
(header_output, decoder_output, decode_block, exec_output) = \
LoadStoreBase(name, Name, sdisp_code, ea_code, memacc_code, mem_flags,
inst_flags, 'Store', exec_template_base='Store')
}};
// Compressed basic instruction class declaration template.
def template CBasicDeclare {{
//
// Static instruction class for "%(mnemonic)s".
//
class %(class_name)s : public %(base_class)s
{
public:
/// Constructor.
%(class_name)s(MachInst machInst);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const override;
};
}};
// Compressed basic instruction class execute method template.
def template CBasicExecute {{
Fault
%(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;
%(op_rd)s;
if (fault == NoFault) {
%(code)s;
if (fault == NoFault) {
%(op_wb)s;
}
}
return fault;
}
std::string
%(class_name)s::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
std::vector<RegId> indices = {%(regs)s};
std::stringstream ss;
ss << mnemonic << ' ';
ss << registerName(indices[0]) << ", ";
ss << registerName(indices[1]);
return ss.str();
}
}};
def format CompressedROp(code, *opt_flags) {{
regs = ['_destRegIdx[0]','_srcRegIdx[1]']
iop = InstObjParams(name, Name, 'RegOp',
{'code': code, 'regs': ','.join(regs)}, opt_flags)
header_output = CBasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = CBasicExecute.subst(iop)
}};
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