1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
|
// -*- mode:c++ -*-
// Copyright (c) 2015 Riscv Developers
// Copyright (c) 2016-2017 The University of Virginia
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Alec Roelke
////////////////////////////////////////////////////////////////////
//
// Floating point operation instructions
//
def template FloatExecute {{
Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;
%(op_rd)s;
if (fault == NoFault) {
switch (ROUND_MODE) {
case 0x0:
std::fesetround(FE_TONEAREST);
break;
case 0x1:
std::fesetround(FE_TOWARDZERO);
break;
case 0x2:
std::fesetround(FE_DOWNWARD);
break;
case 0x3:
std::fesetround(FE_UPWARD);
break;
case 0x4:
// Round to nearest, ties to max magnitude not implemented
fault = make_shared<IllegalFrmFault>(ROUND_MODE);
break;
case 0x7: {
uint8_t frm = xc->readMiscReg(MISCREG_FRM);
switch (frm) {
case 0x0:
std::fesetround(FE_TONEAREST);
break;
case 0x1:
std::fesetround(FE_TOWARDZERO);
break;
case 0x2:
std::fesetround(FE_DOWNWARD);
break;
case 0x3:
std::fesetround(FE_UPWARD);
break;
case 0x4:
// Round to nearest, ties to max magnitude not implemented
fault = make_shared<IllegalFrmFault>(ROUND_MODE);
break;
default:
fault = std::make_shared<IllegalFrmFault>(frm);
break;
}
break;
}
default:
fault = std::make_shared<IllegalFrmFault>(ROUND_MODE);
break;
}
if (fault == NoFault) {
MiscReg FFLAGS = xc->readMiscReg(MISCREG_FFLAGS);
std::feclearexcept(FE_ALL_EXCEPT);
%(code)s;
if (std::fetestexcept(FE_INEXACT)) {
FFLAGS |= FloatInexact;
}
if (std::fetestexcept(FE_UNDERFLOW)) {
FFLAGS |= FloatUnderflow;
}
if (std::fetestexcept(FE_OVERFLOW)) {
FFLAGS |= FloatOverflow;
}
if (std::fetestexcept(FE_DIVBYZERO)) {
FFLAGS |= FloatDivZero;
}
if (std::fetestexcept(FE_INVALID)) {
FFLAGS |= FloatInvalid;
}
xc->setMiscReg(MISCREG_FFLAGS, FFLAGS);
}
if (fault == NoFault) {
%(op_wb)s;
}
}
return fault;
}
}};
def format FPROp(code, *opt_flags) {{
iop = InstObjParams(name, Name, 'RegOp', code, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = FloatExecute.subst(iop)
}};
|