summaryrefslogtreecommitdiff
path: root/src/arch/sparc/isa/formats/branch.isa
blob: 5fb7ade2da5d5b25ec8e5831a9ddaf9f8ffa5fda (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
// Copyright (c) 2006 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Gabe Black
//          Steve Reinhardt

////////////////////////////////////////////////////////////////////
//
// Branch instructions
//

output header {{
        /**
         * Base class for branch operations.
         */
        class Branch : public SparcStaticInst
        {
          protected:
            // Constructor
            Branch(const char *mnem, MachInst _machInst, OpClass __opClass) :
                SparcStaticInst(mnem, _machInst, __opClass)
            {
            }

            std::string generateDisassembly(Addr pc,
                    const SymbolTable *symtab) const;
        };

        /**
         * Base class for branch operations with an immediate displacement.
         */
        class BranchDisp : public Branch
        {
          protected:
            // Constructor
            BranchDisp(const char *mnem, MachInst _machInst,
                    OpClass __opClass) :
                Branch(mnem, _machInst, __opClass)
            {
            }

            std::string generateDisassembly(Addr pc,
                    const SymbolTable *symtab) const;

            int32_t disp;
        };

        /**
         * Base class for branches with n bit displacements.
         */
        template<int bits>
        class BranchNBits : public BranchDisp
        {
          protected:
            // Constructor
            BranchNBits(const char *mnem, MachInst _machInst,
                    OpClass __opClass) :
                BranchDisp(mnem, _machInst, __opClass)
            {
                disp = sext<bits + 2>((_machInst & mask(bits)) << 2);
            }
        };

        /**
         * Base class for 16bit split displacements.
         */
        class BranchSplit : public BranchDisp
        {
          protected:
            // Constructor
            BranchSplit(const char *mnem, MachInst _machInst,
                    OpClass __opClass) :
                BranchDisp(mnem, _machInst, __opClass)
            {
                disp = sext<18>((D16HI << 16) | (D16LO << 2));
            }
        };

        /**
         * Base class for branches that use an immediate and a register to
         * compute their displacements.
         */
        class BranchImm13 : public Branch
        {
          protected:
            // Constructor
            BranchImm13(const char *mnem, MachInst _machInst, OpClass __opClass) :
                Branch(mnem, _machInst, __opClass), imm(sext<13>(SIMM13))
            {
            }

            std::string generateDisassembly(Addr pc,
                    const SymbolTable *symtab) const;

            int32_t imm;
        };
}};

output decoder {{

        template class BranchNBits<19>;

        template class BranchNBits<22>;

        template class BranchNBits<30>;

        std::string Branch::generateDisassembly(Addr pc,
                const SymbolTable *symtab) const
        {
            std::stringstream response;

            printMnemonic(response, mnemonic);
            printRegArray(response, _srcRegIdx, _numSrcRegs);
            if(_numDestRegs && _numSrcRegs)
                    response << ", ";
            printDestReg(response, 0);

            return response.str();
        }

        std::string BranchImm13::generateDisassembly(Addr pc,
                const SymbolTable *symtab) const
        {
            std::stringstream response;

            printMnemonic(response, mnemonic);
            printRegArray(response, _srcRegIdx, _numSrcRegs);
            if(_numSrcRegs > 0)
                response << ", ";
            ccprintf(response, "0x%x", imm);
            if (_numDestRegs > 0)
                response << ", ";
            printDestReg(response, 0);

            return response.str();
        }

        std::string BranchDisp::generateDisassembly(Addr pc,
                const SymbolTable *symtab) const
        {
            std::stringstream response;
            std::string symbol;
            Addr symbolAddr;

            Addr target = disp + pc;

            printMnemonic(response, mnemonic);
            ccprintf(response, "0x%x", target);

            if(symtab->findNearestSymbol(target, symbol, symbolAddr))
            {
                ccprintf(response, " <%s", symbol);
                if(symbolAddr != target)
                    ccprintf(response, "+%d>", target - symbolAddr);
                else
                    ccprintf(response, ">");
            }

            return response.str();
        }
}};

def template BranchExecute {{
        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
                Trace::InstRecord *traceData) const
        {
            //Attempt to execute the instruction
            Fault fault = NoFault;

            %(op_decl)s;
            %(op_rd)s;

            NNPC = xc->readNextNPC();
            %(code)s;

            if(fault == NoFault)
            {
                //Write the resulting state to the execution context
                %(op_wb)s;
            }

            return fault;
        }
}};

let {{
    handle_annul = '''
    {
        if(A)
        {
            NPC = xc->readNextNPC();
            NNPC = NPC + 4;
        }
        else
        {
            NPC = xc->readNextPC();
            NNPC = xc->readNextNPC();
        }
    }'''
}};

// Primary format for branch instructions:
def format Branch(code, *opt_flags) {{
        (usesImm, code, immCode,
         rString, iString) = splitOutImm(code)
        iop = InstObjParams(name, Name, 'Branch', code, opt_flags)
        header_output = BasicDeclare.subst(iop)
        decoder_output = BasicConstructor.subst(iop)
        exec_output = BranchExecute.subst(iop)
        if usesImm:
            imm_iop = InstObjParams(name, Name + 'Imm', 'BranchImm' + iString,
                    immCode, opt_flags)
            header_output += BasicDeclare.subst(imm_iop)
            decoder_output += BasicConstructor.subst(imm_iop)
            exec_output += BranchExecute.subst(imm_iop)
            decode_block = ROrImmDecode.subst(iop)
        else:
            decode_block = BasicDecode.subst(iop)
}};

// Primary format for branch instructions:
def format BranchN(bits, code, *opt_flags) {{
        code = re.sub(r'handle_annul', handle_annul, code)
        codeBlk = CodeBlock(code)
        new_opt_flags = []
        for flag in opt_flags:
            if flag == ',a':
                name += ',a'
                Name += 'Annul'
            else:
                new_opt_flags += flag
        iop = InstObjParams(name, Name, "BranchNBits<%d>" % bits, codeBlk, new_opt_flags)
        header_output = BasicDeclare.subst(iop)
        decoder_output = BasicConstructor.subst(iop)
        exec_output = BranchExecute.subst(iop)
        decode_block = BasicDecode.subst(iop)
}};

// Primary format for branch instructions:
def format BranchSplit(code, *opt_flags) {{
        code = re.sub(r'handle_annul', handle_annul, code)
        codeBlk = CodeBlock(code)
        iop = InstObjParams(name, Name, 'BranchSplit', codeBlk, opt_flags)
        header_output = BasicDeclare.subst(iop)
        decoder_output = BasicConstructor.subst(iop)
        exec_output = BranchExecute.subst(iop)
        decode_block = BasicDecode.subst(iop)
}};