summaryrefslogtreecommitdiff
path: root/src/arch/x86/intmessage.hh
blob: 64e821a419fa230c16d000e0d77d71e8487e55dc (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
/*
 * Copyright (c) 2008 The Regents of The University of Michigan
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * Authors: Gabe Black
 */

#ifndef __ARCH_X86_INTMESSAGE_HH__
#define __ARCH_X86_INTMESSAGE_HH__

#include "arch/x86/x86_traits.hh"
#include "base/bitunion.hh"
#include "mem/packet.hh"
#include "mem/request.hh"
#include "sim/host.hh"

namespace X86ISA
{
    BitUnion32(TriggerIntMessage)
        Bitfield<7, 0> destination;
        Bitfield<15, 8> vector;
        Bitfield<18, 16> deliveryMode;
        Bitfield<19> destMode;
    EndBitUnion(TriggerIntMessage)

    static const Addr TriggerIntOffset = 0;

    static inline PacketPtr
    prepIntRequest(const uint8_t id, Addr offset, Addr size)
    {
        RequestPtr req = new Request(x86InterruptAddress(id, offset),
                                     size, UNCACHEABLE);
        PacketPtr pkt = new Packet(req, MemCmd::MessageReq, Packet::Broadcast);
        pkt->allocate();
        return pkt;
    }

    template<class T>
    PacketPtr
    buildIntRequest(const uint8_t id, T payload, Addr offset, Addr size)
    {
        PacketPtr pkt = prepIntRequest(id, offset, size);
        pkt->set<T>(payload);
        return pkt;
    }

    static inline PacketPtr
    buildIntRequest(const uint8_t id, TriggerIntMessage payload)
    {
        return buildIntRequest(id, payload, TriggerIntOffset,
                sizeof(TriggerIntMessage));
    }

    static inline PacketPtr
    buildIntResponse()
    {
        panic("buildIntResponse not implemented.\n");
    }
}

#endif