path: root/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py

# Copyright (c) 2007 The Hewlett-Packard Development Company
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#
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# commercial advantage.
#
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# covered by patents for commercial use, please contact:
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#
# Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.  Redistributions
# in binary form must reproduce the above copyright notice, this list of
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# other materials provided with the distribution.  Neither the name of
# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
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# this software without specific prior written permission.  No right of
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# notice to acknowledge the contribution from this software where
# applicable, this list of conditions and the disclaimer below.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black

microcode = '''

#
# Byte version of one operand unsigned multiply.
#

def macroop MUL_B_R
{
    mul1u rax, rax, reg, dataSize="2"
};

def macroop MUL_B_M
{
    ld t1, seg, sib, disp
    mul1u rax, rax, t1, dataSize="2"
};

def macroop MUL_B_P
{
    rdip t7
    ld t1, seg, riprel, disp
    mul1u rax, rax, t1, dataSize="2"
};

#
# One operand unsigned multiply.
#

def macroop MUL_R
{
    # We need to store the result of the multiplication in a temporary
    # and then move it later because reg may be rdx. If it is, we can't
    # clobber its old value yet.
    muleh t1, rax, reg
    mulel rax, rax, reg
    mov rdx, rdx, t1
};

def macroop MUL_M
{
    ld t1, seg, sib, disp
    muleh rdx, rax, t1
    mulel rax, rax, t1
};

def macroop MUL_P
{
    rdip t7
    ld t1, seg, riprel, disp
    muleh rdx, rax, t1
    mulel rax, rax, t1
};

#
# Byte version of one operand signed multiply.
#

def macroop IMUL_B_R
{
    mul1s rax, rax, reg, dataSize="2"
};

def macroop IMUL_B_M
{
    ld t1, seg, sib, disp
    mul1s rax, rax, t1, dataSize="2"
};

def macroop IMUL_B_P
{
    rdip t7
    ld t1, seg, riprel, disp
    mul1s rax, rax, t1, dataSize="2"
};

#
# One operand signed multiply.
#

def macroop IMUL_R
{
    mulehs t1, rax, reg
    mulel rax, rax, reg
    mov rdx, rdx, t1
};

def macroop IMUL_M
{
    ld t1, seg, sib, disp
    mulehs rdx, rax, t1
    mulel rax, rax, t1
};

def macroop IMUL_P
{
    rdip t7
    ld t1, seg, riprel, disp
    mulehs rdx, rax, t1
    mulel rax, rax, t1
};

#
# Two operand signed multiply. These should set the CF and OF flags if the
# result is too large for the destination register
#

def macroop IMUL_R_R
{
    mulel reg, reg, regm
};

def macroop IMUL_R_M
{
    ld t1, seg, sib, disp
    mulel reg, reg, t1
};

def macroop IMUL_R_P
{
    rdip t7
    ld t1, seg, riprel, disp
    mulel reg, reg, t1
};

#
# Three operand signed multiply.
#

def macroop IMUL_R_R_I
{
    limm t1, imm
    mulel reg, regm, t1
};

def macroop IMUL_R_M_I
{
    limm t1, imm
    ld t2, seg, sib, disp
    mulel reg, t2, t1
};

def macroop IMUL_R_P_I
{
    rdip t7
    limm t1, imm
    ld t2, seg, riprel
    mulel reg, t2, t1
};

#
# One byte version of unsigned division
#

def macroop DIV_B_R
{
    div1 rax, rax, reg
};

def macroop DIV_B_M
{
    ld t1, seg, sib, disp
    div1 rax, rax, t1
};

def macroop DIV_B_P
{
    rdip t7
    ld t1, seg, riprel, disp
    div1 rax, rax, t1
};

#
# Unsigned division
#

def macroop DIV_R
{
    divr t1, rax, reg
    divq rax, rax, reg
    mov rdx, rdx, t1
};

def macroop DIV_M
{
    ld t1, seg, sib, disp
    divr rdx, rax, t1
    divq rax, rax, t1
};

def macroop DIV_P
{
    rdip t7
    ld t1, seg, riprel, disp
    divr rdx, rax, t1
    divq rax, rax, t1
};

#
# Signed division
#

def macroop IDIV_R
{
    divr t1, rax, reg
    divq rax, rax, reg
    mov rdx, rdx, t1
};

def macroop IDIV_M
{
    ld t1, seg, sib, disp
    divr rdx, rax, t1
    divq rax, rax, t1
};

def macroop IDIV_P
{
    rdip t7
    ld t1, seg, riprel, disp
    divr rdx, rax, t1
    divq rax, rax, t1
};
'''
#let {{
#    class IDIV(Inst):
#	"GenFault ${new UnimpInstFault}"
#}};