1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
|
/*
* Copyright (c) 2001-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Steve Reinhardt
* Lisa Hsu
* Nathan Binkert
* Steve Raasch
*/
#include "cpu/exetrace.hh"
#include <iomanip>
#include "arch/isa_traits.hh"
#include "arch/utility.hh"
#include "base/loader/symtab.hh"
#include "config/the_isa.hh"
#include "cpu/base.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
#include "debug/ExecAll.hh"
#include "enums/OpClass.hh"
using namespace std;
using namespace TheISA;
namespace Trace {
void
ExeTracerRecord::dumpTicks(ostream &outs)
{
ccprintf(outs, "%7d: ", when);
}
void
Trace::ExeTracerRecord::traceInst(const StaticInstPtr &inst, bool ran)
{
ostream &outs = Trace::output();
if (!Debug::ExecUser || !Debug::ExecKernel) {
bool in_user_mode = TheISA::inUserMode(thread);
if (in_user_mode && !Debug::ExecUser) return;
if (!in_user_mode && !Debug::ExecKernel) return;
}
if (Debug::ExecTicks)
dumpTicks(outs);
outs << thread->getCpuPtr()->name() << " ";
if (Debug::ExecAsid)
outs << "A" << dec << TheISA::getExecutingAsid(thread) << " ";
if (Debug::ExecThread)
outs << "T" << thread->threadId() << " : ";
std::string sym_str;
Addr sym_addr;
Addr cur_pc = pc.instAddr();
if (debugSymbolTable && Debug::ExecSymbol &&
(!FullSystem || !inUserMode(thread)) &&
debugSymbolTable->findNearestSymbol(cur_pc, sym_str, sym_addr)) {
if (cur_pc != sym_addr)
sym_str += csprintf("+%d",cur_pc - sym_addr);
outs << "@" << sym_str;
} else {
outs << "0x" << hex << cur_pc;
}
if (inst->isMicroop()) {
outs << "." << setw(2) << dec << pc.microPC();
} else {
outs << " ";
}
outs << " : ";
//
// Print decoded instruction
//
outs << setw(26) << left;
outs << inst->disassemble(cur_pc, debugSymbolTable);
if (ran) {
outs << " : ";
if (Debug::ExecOpClass) {
outs << Enums::OpClassStrings[inst->opClass()] << " : ";
}
if (Debug::ExecResult && !predicate) {
outs << "Predicated False";
}
if (Debug::ExecResult && data_status != DataInvalid) {
ccprintf(outs, " D=%#018x", data.as_int);
}
if (Debug::ExecEffAddr && getMemValid())
outs << " A=0x" << hex << addr;
if (Debug::ExecFetchSeq && fetch_seq_valid)
outs << " FetchSeq=" << dec << fetch_seq;
if (Debug::ExecCPSeq && cp_seq_valid)
outs << " CPSeq=" << dec << cp_seq;
if (Debug::ExecFlags) {
outs << " flags=(";
inst->printFlags(outs, "|");
outs << ")";
}
}
//
// End of line...
//
outs << endl;
}
void
Trace::ExeTracerRecord::dump()
{
/*
* The behavior this check tries to achieve is that if ExecMacro is on,
* the macroop will be printed. If it's on and microops are also on, it's
* printed before the microops start printing to give context. If the
* microops aren't printed, then it's printed only when the final microop
* finishes. Macroops then behave like regular instructions and don't
* complete/print when they fault.
*/
if (Debug::ExecMacro && staticInst->isMicroop() &&
((Debug::ExecMicro &&
macroStaticInst && staticInst->isFirstMicroop()) ||
(!Debug::ExecMicro &&
macroStaticInst && staticInst->isLastMicroop()))) {
traceInst(macroStaticInst, false);
}
if (Debug::ExecMicro || !staticInst->isMicroop()) {
traceInst(staticInst, true);
}
}
} // namespace Trace
////////////////////////////////////////////////////////////////////////
//
// ExeTracer Simulation Object
//
Trace::ExeTracer *
ExeTracerParams::create()
{
return new Trace::ExeTracer(this);
}
|
