1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
|
/*
* Copyright (c) 2007 MIPS Technologies, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Korey Sewell
*
*/
#include <list>
#include <vector>
#include "cpu/inorder/resources/execution_unit.hh"
#include "cpu/inorder/cpu.hh"
#include "cpu/inorder/resource_pool.hh"
#include "debug/InOrderExecute.hh"
#include "debug/InOrderStall.hh"
using namespace std;
using namespace ThePipeline;
ExecutionUnit::ExecutionUnit(string res_name, int res_id, int res_width,
int res_latency, InOrderCPU *_cpu,
ThePipeline::Params *params)
: Resource(res_name, res_id, res_width, res_latency, _cpu),
lastExecuteTick(0), lastControlTick(0), serializeTick(0)
{ }
void
ExecutionUnit::regStats()
{
predictedTakenIncorrect
.name(name() + ".predictedTakenIncorrect")
.desc("Number of Branches Incorrectly Predicted As Taken.");
predictedNotTakenIncorrect
.name(name() + ".predictedNotTakenIncorrect")
.desc("Number of Branches Incorrectly Predicted As Not Taken).");
executions
.name(name() + ".executions")
.desc("Number of Instructions Executed.");
predictedIncorrect
.name(name() + ".mispredicted")
.desc("Number of Branches Incorrectly Predicted");
predictedCorrect
.name(name() + ".predicted")
.desc("Number of Branches Incorrectly Predicted");
mispredictPct
.name(name() + ".mispredictPct")
.desc("Percentage of Incorrect Branches Predicts")
.precision(6);
mispredictPct = (predictedIncorrect /
(predictedCorrect + predictedIncorrect)) * 100;
Resource::regStats();
}
void
ExecutionUnit::execute(int slot_num)
{
ResourceRequest* exec_req = reqs[slot_num];
DynInstPtr inst = reqs[slot_num]->inst;
Fault fault = NoFault;
InstSeqNum seq_num = inst->seqNum;
Tick cur_tick = curTick();
if (cur_tick == serializeTick) {
DPRINTF(InOrderExecute, "Can not execute [tid:%i][sn:%i][PC:%s] %s. "
"All instructions are being serialized this cycle\n",
inst->readTid(), seq_num, inst->pcState(), inst->instName());
exec_req->done(false);
return;
}
switch (exec_req->cmd)
{
case ExecuteInst:
{
if (inst->isNop()) {
DPRINTF(InOrderExecute, "[tid:%i] [sn:%i] [PC:%s] Ignoring execution"
"of %s.\n", inst->readTid(), seq_num, inst->pcState(),
inst->instName());
inst->setExecuted();
exec_req->done();
return;
} else {
DPRINTF(InOrderExecute, "[tid:%i] Executing [sn:%i] [PC:%s] %s.\n",
inst->readTid(), seq_num, inst->pcState(), inst->instName());
}
if (cur_tick != lastExecuteTick) {
lastExecuteTick = cur_tick;
}
assert(!inst->isMemRef());
if (inst->isSerializeAfter()) {
serializeTick = cur_tick;
DPRINTF(InOrderExecute, "Serializing execution after [tid:%i] "
"[sn:%i] [PC:%s] %s.\n", inst->readTid(), seq_num,
inst->pcState(), inst->instName());
}
if (inst->isControl()) {
if (lastControlTick == cur_tick) {
DPRINTF(InOrderExecute, "Can not Execute More than One Control "
"Inst Per Cycle. Blocking Request.\n");
exec_req->done(false);
return;
}
lastControlTick = curTick();
// Evaluate Branch
DPRINTF(IEW, "Pre-Execute %s PC:%s nextPC:%s predPC:%s\n", inst->instName(), inst->pcState(), inst->readPredTarg());
fault = inst->execute();
executions++;
inst->setExecuted();
DPRINTF(IEW, "Post-Execute %s PC:%s nextPC:%s predPC:%s\n", inst->instName(), inst->pcState(), inst->readPredTarg());
if (fault == NoFault) {
// If branch is mispredicted, then signal squash
// throughout all stages behind the pipeline stage
// that got squashed.
if (inst->mispredicted()) {
int stage_num = exec_req->getStageNum();
ThreadID tid = inst->readTid();
// If it's a branch ...
if (inst->isDirectCtrl()) {
assert(!inst->isIndirectCtrl());
TheISA::PCState pc = inst->pcState();
TheISA::advancePC(pc, inst->staticInst);
inst->setPredTarg(pc);
if (inst->predTaken() && inst->isCondDelaySlot()) {
assert(0 && "Not Handling Conditional Delay Slots (1)");
inst->bdelaySeqNum = seq_num;
DPRINTF(InOrderExecute, "[tid:%i]: Conditional"
" branch inst [sn:%i] PC %s mis"
"predicted as taken.\n", tid,
seq_num, inst->pcState());
} else if (!inst->predTaken() && inst->isCondDelaySlot()) {
assert(0 && "Not Handling Conditional Delay Slots (2)");
inst->bdelaySeqNum = seq_num;
inst->procDelaySlotOnMispred = true;
DPRINTF(InOrderExecute, "[tid:%i]: Conditional"
" branch inst [sn:%i] PC %s mis"
"predicted as not taken.\n", tid,
seq_num, inst->pcState());
} else {
inst->bdelaySeqNum = seq_num;
DPRINTF(InOrderExecute, "[tid:%i]: "
"Misprediction detected at "
"[sn:%i] PC %s,\n\t squashing after "
"delay slot instruction [sn:%i].\n",
tid, seq_num, inst->pcState(),
inst->bdelaySeqNum);
DPRINTF(InOrderStall, "STALL: [tid:%i]: Branch"
" misprediction at %s\n",
tid, inst->pcState());
}
DPRINTF(InOrderExecute, "[tid:%i] Redirecting "
"fetch to %s.\n", tid,
inst->readPredTarg());
} else if (inst->isIndirectCtrl()){
TheISA::PCState pc = inst->pcState();
TheISA::advancePC(pc, inst->staticInst);
inst->seqNum = seq_num;
inst->setPredTarg(pc);
inst->bdelaySeqNum = seq_num;
DPRINTF(InOrderExecute, "[tid:%i] Redirecting"
" fetch to %s.\n", tid,
inst->readPredTarg());
} else {
panic("Non-control instruction (%s) mispredict"
"ing?!!", inst->staticInst->getName());
}
DPRINTF(InOrderExecute, "[tid:%i] Squashing will "
"start from stage %i.\n", tid, stage_num);
cpu->pipelineStage[stage_num]->squashDueToBranch(inst,
tid);
inst->squashingStage = stage_num;
// Squash throughout other resources
cpu->resPool->scheduleEvent((InOrderCPU::CPUEventType)
ResourcePool::SquashAll,
inst, 0, 0, tid);
if (inst->predTaken()) {
predictedTakenIncorrect++;
DPRINTF(InOrderExecute, "[tid:%i] [sn:%i] %s ..."
"PC %s ... Mispredicts! (Taken)\n",
tid, inst->seqNum,
inst->staticInst->disassemble(
inst->instAddr()),
inst->pcState());
} else {
predictedNotTakenIncorrect++;
DPRINTF(InOrderExecute, "[tid:%i] [sn:%i] %s ..."
"PC %s ... Mispredicts! (Not Taken)\n",
tid, inst->seqNum,
inst->staticInst->disassemble(
inst->instAddr()),
inst->pcState());
}
predictedIncorrect++;
} else {
DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: Prediction"
"Correct.\n", inst->readTid(), seq_num);
predictedCorrect++;
}
exec_req->done();
} else {
warn("inst [sn:%i] had a %s fault", seq_num, fault->name());
exec_req->done();
}
} else {
// Regular ALU instruction
fault = inst->execute();
executions++;
if (fault == NoFault) {
inst->setExecuted();
DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: The result "
"of execution is 0x%x.\n", inst->readTid(),
seq_num,
(inst->resultType(0) == InOrderDynInst::Float) ?
inst->readFloatResult(0) : inst->readIntResult(0));
} else {
DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: had a %s "
"fault.\n", inst->readTid(), seq_num, fault->name());
inst->fault = fault;
}
exec_req->done();
}
}
break;
default:
fatal("Unrecognized command to %s", resName);
}
}
|