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# -*- mode:python -*-
# Copyright (c) 2006 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Nathan Binkert
import sys
Import('*')
if 'O3CPU' in env['CPU_MODELS'] or 'OzoneCPU' in env['CPU_MODELS']:
Source('2bit_local_pred.cc')
Source('btb.cc')
Source('ras.cc')
Source('tournament_pred.cc')
TraceFlag('CommitRate')
TraceFlag('IEW')
TraceFlag('IQ')
if 'O3CPU' in env['CPU_MODELS']:
SimObject('FUPool.py')
SimObject('FuncUnitConfig.py')
SimObject('O3CPU.py')
Source('base_dyn_inst.cc')
Source('bpred_unit.cc')
Source('commit.cc')
Source('cpu.cc')
Source('decode.cc')
Source('fetch.cc')
Source('free_list.cc')
Source('fu_pool.cc')
Source('iew.cc')
Source('inst_queue.cc')
Source('lsq.cc')
Source('lsq_unit.cc')
Source('mem_dep_unit.cc')
Source('rename.cc')
Source('rename_map.cc')
Source('rob.cc')
Source('scoreboard.cc')
Source('store_set.cc')
TraceFlag('FreeList')
TraceFlag('LSQ')
TraceFlag('LSQUnit')
TraceFlag('MemDepUnit')
TraceFlag('O3CPU')
TraceFlag('ROB')
TraceFlag('Rename')
TraceFlag('Scoreboard')
TraceFlag('StoreSet')
TraceFlag('Writeback')
CompoundFlag('O3CPUAll', [ 'Fetch', 'Decode', 'Rename', 'IEW', 'Commit',
'IQ', 'ROB', 'FreeList', 'LSQ', 'LSQUnit', 'StoreSet', 'MemDepUnit',
'DynInst', 'O3CPU', 'Activity', 'Scoreboard', 'Writeback' ])
if env['TARGET_ISA'] == 'alpha':
Source('alpha/cpu.cc')
Source('alpha/cpu_builder.cc')
Source('alpha/dyn_inst.cc')
Source('alpha/thread_context.cc')
elif env['TARGET_ISA'] == 'mips':
Source('mips/cpu.cc')
Source('mips/cpu_builder.cc')
Source('mips/dyn_inst.cc')
Source('mips/thread_context.cc')
elif env['TARGET_ISA'] == 'sparc':
Source('sparc/cpu.cc')
Source('sparc/cpu_builder.cc')
Source('sparc/dyn_inst.cc')
Source('sparc/thread_context.cc')
else:
sys.exit('O3 CPU does not support the \'%s\' ISA' % env['TARGET_ISA'])
if env['USE_CHECKER']:
SimObject('O3Checker.py')
Source('checker_builder.cc')
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