summaryrefslogtreecommitdiff
path: root/src/dev/arm/pl011.cc
blob: f0c3d2d9871628ed595ebbe9a94dadbbf896586e (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
/*
 * Copyright (c) 2010, 2015 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Copyright (c) 2005 The Regents of The University of Michigan
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * Authors: Ali Saidi
 *          Andreas Sandberg
 */

#include "dev/arm/pl011.hh"

#include "base/trace.hh"
#include "debug/Checkpoint.hh"
#include "debug/Uart.hh"
#include "dev/arm/amba_device.hh"
#include "dev/arm/base_gic.hh"
#include "dev/terminal.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/sim_exit.hh"
#include "params/Pl011.hh"

Pl011::Pl011(const Pl011Params *p)
    : Uart(p, 0xfff),
      intEvent(this),
      control(0x300), fbrd(0), ibrd(0), lcrh(0), ifls(0x12),
      imsc(0), rawInt(0),
      gic(p->gic), endOnEOT(p->end_on_eot), intNum(p->int_num),
      intDelay(p->int_delay)
{
}

Tick
Pl011::read(PacketPtr pkt)
{
    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);

    Addr daddr = pkt->getAddr() - pioAddr;

    DPRINTF(Uart, " read register %#x size=%d\n", daddr, pkt->getSize());

    // use a temporary data since the uart registers are read/written with
    // different size operations
    //
    uint32_t data = 0;

    switch(daddr) {
      case UART_DR:
        data = 0;
        if (term->dataAvailable()) {
            data = term->in();
            // Since we don't simulate a FIFO for incoming data, we
            // assume it's empty and clear RXINTR and RTINTR.
            clearInterrupts(UART_RXINTR | UART_RTINTR);
        }
        break;
      case UART_FR:
        data =
            UART_FR_CTS | // Clear To Send
            (!term->dataAvailable() ? UART_FR_RXFE : 0) | // RX FIFO Empty
            UART_FR_TXFE; // TX FIFO empty

        DPRINTF(Uart,
                "Reading FR register as %#x rawInt=0x%x "
                "imsc=0x%x maskInt=0x%x\n",
                data, rawInt, imsc, maskInt());
        break;
      case UART_CR:
        data = control;
        break;
      case UART_IBRD:
        data = ibrd;
        break;
      case UART_FBRD:
        data = fbrd;
        break;
      case UART_LCRH:
        data = lcrh;
        break;
      case UART_IFLS:
        data = ifls;
        break;
      case UART_IMSC:
        data = imsc;
        break;
      case UART_RIS:
        data = rawInt;
        DPRINTF(Uart, "Reading Raw Int status as 0x%x\n", rawInt);
        break;
      case UART_MIS:
        DPRINTF(Uart, "Reading Masked Int status as 0x%x\n", maskInt());
        data = maskInt();
        break;
      default:
        if (readId(pkt, AMBA_ID, pioAddr)) {
            // Hack for variable size accesses
            data = pkt->get<uint32_t>();
            break;
        }

        panic("Tried to read PL011 at offset %#x that doesn't exist\n", daddr);
        break;
    }

    switch(pkt->getSize()) {
      case 1:
        pkt->set<uint8_t>(data);
        break;
      case 2:
        pkt->set<uint16_t>(data);
        break;
      case 4:
        pkt->set<uint32_t>(data);
        break;
      default:
        panic("Uart read size too big?\n");
        break;
    }


    pkt->makeAtomicResponse();
    return pioDelay;
}

Tick
Pl011::write(PacketPtr pkt)
{

    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);

    Addr daddr = pkt->getAddr() - pioAddr;

    DPRINTF(Uart, " write register %#x value %#x size=%d\n", daddr,
            pkt->get<uint8_t>(), pkt->getSize());

    // use a temporary data since the uart registers are read/written with
    // different size operations
    //
    uint32_t data = 0;

    switch(pkt->getSize()) {
      case 1:
        data = pkt->get<uint8_t>();
        break;
      case 2:
        data = pkt->get<uint16_t>();
        break;
      case 4:
        data = pkt->get<uint32_t>();
        break;
      default:
        panic("Uart write size too big?\n");
        break;
    }


    switch (daddr) {
        case UART_DR:
          if ((data & 0xFF) == 0x04 && endOnEOT)
            exitSimLoop("UART received EOT", 0);

        term->out(data & 0xFF);
        // We're supposed to clear TXINTR when this register is
        // written to, however. since we're also infinitely fast, we
        // need to immediately raise it again.
        clearInterrupts(UART_TXINTR);
        raiseInterrupts(UART_TXINTR);
        break;
      case UART_CR:
        control = data;
        break;
      case UART_IBRD:
        ibrd = data;
        break;
      case UART_FBRD:
        fbrd = data;
        break;
      case UART_LCRH:
        lcrh = data;
        break;
      case UART_IFLS:
        ifls = data;
        break;
      case UART_IMSC:
        DPRINTF(Uart, "Setting interrupt mask 0x%x\n", data);
        setInterruptMask(data);
        break;

      case UART_ICR:
        DPRINTF(Uart, "Clearing interrupts 0x%x\n", data);
        clearInterrupts(data);
        break;
      default:
        panic("Tried to write PL011 at offset %#x that doesn't exist\n", daddr);
        break;
    }
    pkt->makeAtomicResponse();
    return pioDelay;
}

void
Pl011::dataAvailable()
{
    /*@todo ignore the fifo, just say we have data now
     * We might want to fix this, or we might not care */
    DPRINTF(Uart, "Data available, scheduling interrupt\n");
    raiseInterrupts(UART_RXINTR | UART_RTINTR);
}

void
Pl011::generateInterrupt()
{
    DPRINTF(Uart, "Generate Interrupt: imsc=0x%x rawInt=0x%x maskInt=0x%x\n",
            imsc, rawInt, maskInt());

    if (maskInt()) {
        gic->sendInt(intNum);
        DPRINTF(Uart, " -- Generated\n");
    }
}

void
Pl011::setInterrupts(uint16_t ints, uint16_t mask)
{
    const bool old_ints(!!maskInt());

    imsc = mask;
    rawInt = ints;

    if (!old_ints && maskInt()) {
        if (!intEvent.scheduled())
            schedule(intEvent, curTick() + intDelay);
    } else if (old_ints && !maskInt()) {
        gic->clearInt(intNum);
    }
}



void
Pl011::serialize(CheckpointOut &cp) const
{
    DPRINTF(Checkpoint, "Serializing Arm PL011\n");
    SERIALIZE_SCALAR(control);
    SERIALIZE_SCALAR(fbrd);
    SERIALIZE_SCALAR(ibrd);
    SERIALIZE_SCALAR(lcrh);
    SERIALIZE_SCALAR(ifls);

    // Preserve backwards compatibility by giving these silly names.
    paramOut(cp, "imsc_serial", imsc);
    paramOut(cp, "rawInt_serial", rawInt);
}

void
Pl011::unserialize(CheckpointIn &cp)
{
    DPRINTF(Checkpoint, "Unserializing Arm PL011\n");

    UNSERIALIZE_SCALAR(control);
    UNSERIALIZE_SCALAR(fbrd);
    UNSERIALIZE_SCALAR(ibrd);
    UNSERIALIZE_SCALAR(lcrh);
    UNSERIALIZE_SCALAR(ifls);

    // Preserve backwards compatibility by giving these silly names.
    paramIn(cp, "imsc_serial", imsc);
    paramIn(cp, "rawInt_serial", rawInt);
}

Pl011 *
Pl011Params::create()
{
    return new Pl011(this);
}