1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
|
/*
* Copyright (c) 2013, 2018-2019 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Stan Czerniawski
*/
#ifndef __DEV_ARM_SMMU_V3_PORTS_HH__
#define __DEV_ARM_SMMU_V3_PORTS_HH__
#include "mem/qport.hh"
#include "mem/tport.hh"
class SMMUv3;
class SMMUv3SlaveInterface;
class SMMUMasterPort : public MasterPort
{
protected:
SMMUv3 &smmu;
virtual bool recvTimingResp(PacketPtr pkt);
virtual void recvReqRetry();
public:
SMMUMasterPort(const std::string &_name, SMMUv3 &_smmu);
virtual ~SMMUMasterPort() {}
};
// Separate master port to send MMU initiated requests on
class SMMUMasterTableWalkPort : public MasterPort
{
protected:
SMMUv3 &smmu;
virtual bool recvTimingResp(PacketPtr pkt);
virtual void recvReqRetry();
public:
SMMUMasterTableWalkPort(const std::string &_name, SMMUv3 &_smmu);
virtual ~SMMUMasterTableWalkPort() {}
};
class SMMUSlavePort : public QueuedSlavePort
{
protected:
SMMUv3SlaveInterface &ifc;
RespPacketQueue respQueue;
virtual void recvFunctional(PacketPtr pkt);
virtual Tick recvAtomic(PacketPtr pkt);
virtual bool recvTimingReq(PacketPtr pkt);
public:
SMMUSlavePort(const std::string &_name,
SMMUv3SlaveInterface &_ifc,
PortID _id = InvalidPortID);
virtual ~SMMUSlavePort() {}
virtual AddrRangeList getAddrRanges() const
{ return AddrRangeList { AddrRange(0, UINT64_MAX) }; }
};
class SMMUControlPort : public SimpleTimingPort
{
protected:
SMMUv3 &smmu;
AddrRange addrRange;
virtual Tick recvAtomic(PacketPtr pkt);
virtual AddrRangeList getAddrRanges() const;
public:
SMMUControlPort(const std::string &_name, SMMUv3 &_smmu,
AddrRange _addrRange);
virtual ~SMMUControlPort() {}
};
class SMMUATSMasterPort : public QueuedMasterPort
{
protected:
SMMUv3SlaveInterface &ifc;
ReqPacketQueue reqQueue;
SnoopRespPacketQueue snoopRespQueue;
virtual bool recvTimingResp(PacketPtr pkt);
public:
SMMUATSMasterPort(const std::string &_name, SMMUv3SlaveInterface &_ifc);
virtual ~SMMUATSMasterPort() {}
};
class SMMUATSSlavePort : public QueuedSlavePort
{
protected:
SMMUv3SlaveInterface &ifc;
RespPacketQueue respQueue;
virtual void recvFunctional(PacketPtr pkt);
virtual Tick recvAtomic(PacketPtr pkt);
virtual bool recvTimingReq(PacketPtr pkt);
virtual AddrRangeList getAddrRanges() const
{ return AddrRangeList(); }
public:
SMMUATSSlavePort(const std::string &_name, SMMUv3SlaveInterface &_ifc);
virtual ~SMMUATSSlavePort() {}
};
#endif /* __DEV_ARM_SMMU_V3_PORTS_HH__ */
|
