1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
|
/*
* Copyright (c) 2004-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Ali Saidi
* Rick Strong
*/
/** @file
* Emulation of the Malta CChip CSRs
*/
#ifndef __MALTA_CCHIP_HH__
#define __MALTA_CCHIP_HH__
#include "dev/mips/malta.hh"
#include "dev/io_device.hh"
#include "params/MaltaCChip.hh"
/**
* Malta CChip CSR Emulation. This device includes all the interrupt
* handling code for the chipset.
*/
class MaltaCChip : public BasicPioDevice
{
protected:
/**
* pointer to the malta object.
* This is our access to all the other malta
* devices.
*/
Malta *malta;
/**
* The dims are device interrupt mask registers.
* One exists for each CPU, the DRIR X DIM = DIR
*/
//uint64_t dim[Malta::Max_CPUs];
/**
* The dirs are device interrupt registers.
* One exists for each CPU, the DRIR X DIM = DIR
*/
//uint64_t dir[Malta::Max_CPUs];
/**
* This register contains bits for each PCI interrupt
* that can occur.
*/
//uint64_t drir;
/** Indicator of which CPUs have an IPI interrupt */
//uint64_t ipint;
/** Indicator of which CPUs have an RTC interrupt */
//uint64_t itint;
public:
typedef MaltaCChipParams Params;
const Params *
params() const
{
return dynamic_cast<const Params *>(_params);
}
/**
* Initialize the Malta CChip by setting all of the
* device register to 0.
* @param p params struct
*/
MaltaCChip(Params *p);
virtual Tick read(PacketPtr pkt);
virtual Tick write(PacketPtr pkt);
/**
* post an RTC interrupt to the CPU
*/
void postRTC();
/**
* post an interrupt to the CPU.
* @param interrupt the interrupt number to post (0-7)
*/
void postIntr(uint32_t interrupt);
/**
* clear an interrupt previously posted to the CPU.
* @param interrupt the interrupt number to post (0-7)
*/
void clearIntr(uint32_t interrupt);
/**
* post an ipi interrupt to the CPU.
* @param ipintr the cpu number to clear(bitvector)
*/
void clearIPI(uint64_t ipintr);
/**
* clear a timer interrupt previously posted to the CPU.
* @param itintr the cpu number to clear(bitvector)
*/
void clearITI(uint64_t itintr);
/**
* request an interrupt be posted to the CPU.
* @param ipreq the cpu number to interrupt(bitvector)
*/
void reqIPI(uint64_t ipreq);
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
};
#endif // __MALTA_CCHIP_HH__
|
