1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
|
/*
* Copyright (c) 2004-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#include "debug/CMOS.hh"
#include "dev/x86/cmos.hh"
#include "dev/x86/intdev.hh"
#include "mem/packet_access.hh"
void
X86ISA::Cmos::X86RTC::handleEvent()
{
assert(intPin);
intPin->raise();
//XXX This is a hack.
intPin->lower();
}
Tick
X86ISA::Cmos::read(PacketPtr pkt)
{
assert(pkt->getSize() == 1);
switch(pkt->getAddr() - pioAddr)
{
case 0x0:
pkt->set(address);
break;
case 0x1:
pkt->set(readRegister(address));
break;
default:
panic("Read from undefined CMOS port.\n");
}
pkt->makeAtomicResponse();
return latency;
}
Tick
X86ISA::Cmos::write(PacketPtr pkt)
{
assert(pkt->getSize() == 1);
switch(pkt->getAddr() - pioAddr)
{
case 0x0:
address = pkt->get<uint8_t>();
break;
case 0x1:
writeRegister(address, pkt->get<uint8_t>());
break;
default:
panic("Write to undefined CMOS port.\n");
}
pkt->makeAtomicResponse();
return latency;
}
uint8_t
X86ISA::Cmos::readRegister(uint8_t reg)
{
assert(reg < numRegs);
uint8_t val;
if (reg <= 0xD) {
val = rtc.readData(reg);
DPRINTF(CMOS,
"Reading CMOS RTC reg %x as %x.\n", reg, val);
} else {
val = regs[reg];
DPRINTF(CMOS,
"Reading non-volitile CMOS address %x as %x.\n", reg, val);
}
return val;
}
void
X86ISA::Cmos::writeRegister(uint8_t reg, uint8_t val)
{
assert(reg < numRegs);
if (reg <= 0xD) {
DPRINTF(CMOS, "Writing CMOS RTC reg %x with %x.\n",
reg, val);
rtc.writeData(reg, val);
} else {
DPRINTF(CMOS, "Writing non-volitile CMOS address %x with %x.\n",
reg, val);
regs[reg] = val;
}
}
void
X86ISA::Cmos::serialize(std::ostream &os)
{
SERIALIZE_SCALAR(address);
SERIALIZE_ARRAY(regs, numRegs);
// Serialize the timer
rtc.serialize("rtc", os);
}
void
X86ISA::Cmos::unserialize(Checkpoint *cp, const std::string §ion)
{
UNSERIALIZE_SCALAR(address);
UNSERIALIZE_ARRAY(regs, numRegs);
// Serialize the timer
rtc.unserialize("rtc", cp, section);
}
X86ISA::Cmos *
CmosParams::create()
{
return new X86ISA::Cmos(this);
}
|
