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/*
* Copyright (c) 2016 Jason Lowe-Power
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Jason Lowe-Power
*/
#ifndef __LEARNING_GEM5_SIMPLE_OBJECT_HH__
#define __LEARNING_GEM5_SIMPLE_OBJECT_HH__
#include "mem/port.hh"
#include "params/SimpleObject.hh"
#include "sim/sim_object.hh"
class SimpleObject : public SimObject
{
class SimplePort: public MasterPort
{
public:
// these virtual functions must be implemented
virtual bool recvTimingResp(PacketPtr pkt) override;
virtual void recvReqRetry()
{
fatal("SimplePort::recvReqRetry not implemented!\n");
}
// SimplePort::SimplePort() is deleted
SimplePort(const std::string &name, SimpleObject *owner):
MasterPort(name, owner)
{
}
};
MasterID masterId;
SimplePort memPort;
bool isread;
EventFunctionWrapper event;
public:
SimpleObject(SimpleObjectParams *p);
virtual Port &getPort(const std::string &if_name,
PortID idx=InvalidPortID) override
{
if (if_name == "mem_side")
return memPort;
return SimpleObject::getPort(if_name, idx);
}
virtual void startup() override;
void processEvent();
void readAtomic();
void readTiming();
void writeAtomic();
};
#endif // __LEARNING_GEM5_SIMPLE_OBJECT_HH__
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