1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
|
/*
* Copyright (c) 2002-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Erik Hallnor
*/
/**
* @file
* Miss Status and Handling Register (MSHR) declaration.
*/
#ifndef __MSHR_HH__
#define __MSHR_HH__
#include <list>
#include "mem/packet.hh"
class CacheBlk;
class MSHRQueue;
/**
* Miss Status and handling Register. This class keeps all the information
* needed to handle a cache miss including a list of target requests.
*/
class MSHR : public Packet::SenderState
{
public:
class Target {
public:
Tick recvTime; //!< Time when request was received (for stats)
Tick readyTime; //!< Time when request is ready to be serviced
Counter order; //!< Global order (for memory consistency mgmt)
PacketPtr pkt; //!< Pending request packet.
bool cpuSide; //!< Did request come from cpu side or mem side?
bool isCpuSide() { return cpuSide; }
Target(PacketPtr _pkt, Tick _readyTime, Counter _order, bool _cpuSide)
: recvTime(curTick), readyTime(_readyTime), order(_order),
pkt(_pkt), cpuSide(_cpuSide)
{}
};
/** Defines the Data structure of the MSHR targetlist. */
typedef std::list<Target> TargetList;
/** Target list iterator. */
typedef std::list<Target>::iterator TargetListIterator;
/** A list of MSHRs. */
typedef std::list<MSHR *> List;
/** MSHR list iterator. */
typedef List::iterator Iterator;
/** MSHR list const_iterator. */
typedef List::const_iterator ConstIterator;
/** Pointer to queue containing this MSHR. */
MSHRQueue *queue;
/** Cycle when ready to issue */
Tick readyTime;
/** Order number assigned by the miss queue. */
Counter order;
/** Address of the request. */
Addr addr;
/** Size of the request. */
int size;
/** True if the request has been sent to the bus. */
bool inService;
/** True if we will be putting the returned block in the cache */
bool isCacheFill;
/** True if we need to get an exclusive copy of the block. */
bool needsExclusive;
/** True if the request is uncacheable */
bool _isUncacheable;
bool deferredNeedsExclusive;
bool pendingInvalidate;
bool pendingShared;
/** Thread number of the miss. */
short threadNum;
/** The number of currently allocated targets. */
short ntargets;
/** Data buffer (if needed). Currently used only for pending
* upgrade handling. */
uint8_t *data;
/**
* Pointer to this MSHR on the ready list.
* @sa MissQueue, MSHRQueue::readyList
*/
Iterator readyIter;
/**
* Pointer to this MSHR on the allocated list.
* @sa MissQueue, MSHRQueue::allocatedList
*/
Iterator allocIter;
private:
/** List of all requests that match the address */
TargetList targets;
TargetList deferredTargets;
public:
bool isUncacheable() { return _isUncacheable; }
/**
* Allocate a miss to this MSHR.
* @param cmd The requesting command.
* @param addr The address of the miss.
* @param asid The address space id of the miss.
* @param size The number of bytes to request.
* @param pkt The original miss.
*/
void allocate(Addr addr, int size, PacketPtr pkt,
Tick when, Counter _order);
/**
* Mark this MSHR as free.
*/
void deallocate();
/**
* Add a request to the list of targets.
* @param target The target.
*/
void allocateTarget(PacketPtr target, Tick when, Counter order);
void allocateSnoopTarget(PacketPtr target, Tick when, Counter order);
/** A simple constructor. */
MSHR();
/** A simple destructor. */
~MSHR();
/**
* Returns the current number of allocated targets.
* @return The current number of allocated targets.
*/
int getNumTargets() { return ntargets; }
/**
* Returns a pointer to the target list.
* @return a pointer to the target list.
*/
TargetList* getTargetList() { return &targets; }
/**
* Returns true if there are targets left.
* @return true if there are targets
*/
bool hasTargets() { return !targets.empty(); }
/**
* Returns a reference to the first target.
* @return A pointer to the first target.
*/
Target *getTarget() { assert(hasTargets()); return &targets.front(); }
/**
* Pop first target.
*/
void popTarget()
{
--ntargets;
targets.pop_front();
}
bool isSimpleForward()
{
if (getNumTargets() != 1)
return false;
Target *tgt = getTarget();
return tgt->isCpuSide() && !tgt->pkt->needsResponse();
}
bool promoteDeferredTargets();
void handleFill(Packet *pkt, CacheBlk *blk);
/**
* Prints the contents of this MSHR to stderr.
*/
void dump();
};
#endif //__MSHR_HH__
|
