1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
|
/*
* Copyright (c) 2011-2015 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Copyright (c) 2002-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Ron Dreslinski
* Ali Saidi
* Andreas Hansson
* William Wang
*/
/**
* @file
* Declaration of a non-coherent crossbar.
*/
#ifndef __MEM_NONCOHERENT_XBAR_HH__
#define __MEM_NONCOHERENT_XBAR_HH__
#include "mem/xbar.hh"
#include "params/NoncoherentXBar.hh"
/**
* A non-coherent crossbar connects a number of non-snooping masters
* and slaves, and routes the request and response packets based on
* the address. The request packets issued by the master connected to
* a non-coherent crossbar could still snoop in caches attached to a
* coherent crossbar, as is the case with the I/O bus and memory bus
* in most system configurations. No snoops will, however, reach any
* master on the non-coherent crossbar itself.
*
* The non-coherent crossbar can be used as a template for modelling
* PCIe, and non-coherent AMBA and OCP buses, and is typically used
* for the I/O buses.
*/
class NoncoherentXBar : public BaseXBar
{
protected:
/**
* Declare the layers of this crossbar, one vector for requests
* and one for responses.
*/
std::vector<ReqLayer*> reqLayers;
std::vector<RespLayer*> respLayers;
/**
* Declaration of the non-coherent crossbar slave port type, one
* will be instantiated for each of the master ports connecting to
* the crossbar.
*/
class NoncoherentXBarSlavePort : public QueuedSlavePort
{
private:
/** A reference to the crossbar to which this port belongs. */
NoncoherentXBar &xbar;
/** A normal packet queue used to store responses. */
RespPacketQueue queue;
public:
NoncoherentXBarSlavePort(const std::string &_name,
NoncoherentXBar &_xbar, PortID _id)
: QueuedSlavePort(_name, &_xbar, queue, _id), xbar(_xbar),
queue(_xbar, *this)
{ }
protected:
bool
recvTimingReq(PacketPtr pkt) override
{
return xbar.recvTimingReq(pkt, id);
}
Tick
recvAtomic(PacketPtr pkt) override
{
return xbar.recvAtomic(pkt, id);
}
void
recvFunctional(PacketPtr pkt) override
{
xbar.recvFunctional(pkt, id);
}
AddrRangeList
getAddrRanges() const override
{
return xbar.getAddrRanges();
}
};
/**
* Declaration of the crossbar master port type, one will be
* instantiated for each of the slave ports connecting to the
* crossbar.
*/
class NoncoherentXBarMasterPort : public MasterPort
{
private:
/** A reference to the crossbar to which this port belongs. */
NoncoherentXBar &xbar;
public:
NoncoherentXBarMasterPort(const std::string &_name,
NoncoherentXBar &_xbar, PortID _id)
: MasterPort(_name, &_xbar, _id), xbar(_xbar)
{ }
protected:
bool
recvTimingResp(PacketPtr pkt) override
{
return xbar.recvTimingResp(pkt, id);
}
void
recvRangeChange() override
{
xbar.recvRangeChange(id);
}
void
recvReqRetry() override
{
xbar.recvReqRetry(id);
}
};
virtual bool recvTimingReq(PacketPtr pkt, PortID slave_port_id);
virtual bool recvTimingResp(PacketPtr pkt, PortID master_port_id);
void recvReqRetry(PortID master_port_id);
Tick recvAtomic(PacketPtr pkt, PortID slave_port_id);
void recvFunctional(PacketPtr pkt, PortID slave_port_id);
public:
NoncoherentXBar(const NoncoherentXBarParams *p);
virtual ~NoncoherentXBar();
void regStats() override;
Stats::Scalar totPktSize;
};
#endif //__MEM_NONCOHERENT_XBAR_HH__
|
