summaryrefslogtreecommitdiff
path: root/src/mem/protocol/RubySlicc_ComponentMapping.sm
blob: 022bb6862c99fa3fa738b853c132d603965260cd (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

/*
 * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

// Mapping functions

// NodeID map_address_to_node(Address addr);
MachineID map_Address_to_DMA(Address addr);
MachineID map_Address_to_Directory(Address addr);
NodeID map_Address_to_DirectoryNode(Address addr);
MachineID map_Address_to_CentralArbiterNode(Address addr);
NodeID oldmap_L1RubyNode_to_L2Cache(Address addr, NodeID L1RubyNode);
MachineID map_L1CacheMachId_to_L2Cache(Address addr, MachineID L1CacheMachId);
MachineID map_L2ChipId_to_L2Cache(Address addr, NodeID L2ChipId);
// MachineID map_L1RubyNode_to_Arb(NodeID L1RubyNode);

MachineID getL1MachineID(NodeID L1RubyNode);
NodeID getChipID(MachineID L2machID);
MachineID getCollectorDest(MachineID L1machID);
MachineID getCollectorL1Cache(MachineID colID);
NetDest getMultiStaticL2BankNetDest(Address addr, Set sharers);
bool isL1OnChip(MachineID L1machID, NodeID L2NodeID);
bool isL2OnChip(MachineID L2machID, NodeID L2NodeID);

int getNumBanksInBankSet();
NodeID machineIDToNodeID(MachineID machID);
NodeID machineIDToVersion(MachineID machID);
MachineType machineIDToMachineType(MachineID machID);
NodeID L1CacheMachIDToProcessorNum(MachineID machID);
NodeID L2CacheMachIDToChipID(MachineID machID);
Set getOtherLocalL1IDs(MachineID L1);
Set getLocalL1IDs(MachineID L1);
Set getExternalL1IDs(MachineID L1);
NetDest getAllPertinentL2Banks(Address addr);
bool isLocalProcessor(MachineID thisId, MachineID tarId);

GenericMachineType ConvertMachToGenericMach(MachineType machType);