summaryrefslogtreecommitdiff
path: root/src/mem/protocol/RubySlicc_Exports.sm
blob: 1d591482de8c402b11659aedee82b0cc03f5200c (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
/*
 * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood
 * Copyright (c) 2011 Advanced Micro Devices, Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

// Declarations of external types that are common to all protocols
external_type(int, primitive="yes", default="0");
external_type(bool, primitive="yes", default="false");
external_type(std::string, primitive="yes");
external_type(uint32_t, primitive="yes");
external_type(uint64, primitive="yes");
external_type(PacketPtr, primitive="yes");
external_type(Packet, primitive="yes");
external_type(Address);
external_type(Cycles, primitive="yes", default="Cycles(0)");

structure(DataBlock, external = "yes", desc="..."){
  void clear();
  void copyPartial(DataBlock, int, int);
}

bool testAndRead(Address addr, DataBlock datablk, Packet *pkt);
bool testAndWrite(Address addr, DataBlock datablk, Packet *pkt);

// AccessPermission
// The following five states define the access permission of all memory blocks.
// These permissions have multiple uses.  They coordinate locking and 
// synchronization primitives, as well as enable functional accesses.
// One should not need to add any additional permission values and it is very
// risky to do so.
enumeration(AccessPermission, desc="...", default="AccessPermission_NotPresent") {
  // Valid data
  Read_Only,  desc="block is Read Only (modulo functional writes)";
  Read_Write, desc="block is Read/Write";

  // Possibly Invalid data
  // The maybe stale permission indicates that accordingly to the protocol, 
  // there is no guarantee the block contains valid data.  However, functional
  // writes should update the block because a dataless PUT request may
  // revalidate the block's data.
  Maybe_Stale, desc="block can be stale or revalidated by a dataless PUT";
  // In Broadcast/Snoop protocols, memory has no idea if it is exclusive owner
  // or not of a block, making it hard to make the logic of having only one
  // read_write block in the system impossible. This is to allow the memory to
  // say, "I have the block" and for the RubyPort logic to know that this is a
  // last-resort block if there are no writable copies in the caching hierarchy.
  // This is not supposed to be used in directory or token protocols where
  // memory/NB has an idea of what is going on in the whole system.
  Backing_Store, desc="for memory in Broadcast/Snoop protocols";

  // Invalid data
  Invalid,    desc="block is in an Invalid base state";
  NotPresent, desc="block is NotPresent";
  Busy,       desc="block is in a transient state, currently invalid";
}

// TesterStatus
enumeration(TesterStatus, desc="...") {
  Idle,            desc="Idle";
  Action_Pending,  desc="Action Pending";
  Ready,           desc="Ready";
  Check_Pending,   desc="Check Pending";
}

// InvalidateGeneratorStatus
enumeration(InvalidateGeneratorStatus, desc="...") {
  Load_Waiting,    desc="Load waiting to be issued";
  Load_Pending,    desc="Load issued";
  Inv_Waiting,     desc="Store (invalidate) waiting to be issued";
  Inv_Pending,     desc="Store (invalidate) issued";
}

// SeriesRequestGeneratorStatus
enumeration(SeriesRequestGeneratorStatus, desc="...") {
  Thinking,        desc="Doing work before next action";
  Request_Pending, desc="Request pending";
}

// LockStatus
enumeration(LockStatus, desc="...") {
  Unlocked,        desc="Lock is not held";
  Locked,          desc="Lock is held";
}

// SequencerStatus
enumeration(SequencerStatus, desc="...") {
  Idle,            desc="Idle";
  Pending,         desc="Pending";
}

enumeration(TransitionResult, desc="...") {
  Valid,         desc="Valid transition";
  ResourceStall, desc="Stalled due to insufficient resources";
  ProtocolStall, desc="Protocol specified stall";
  Reject,        desc="Rejected because of a type mismatch";
}

// RubyRequestType
enumeration(RubyRequestType, desc="...", default="RubyRequestType_NULL") {
  LD,                desc="Load";
  ST,                desc="Store";
  ATOMIC,            desc="Atomic Load/Store";
  IFETCH,            desc="Instruction fetch";
  IO,                desc="I/O";
  REPLACEMENT,       desc="Replacement";
  Load_Linked,       desc="";
  Store_Conditional, desc="";
  RMW_Read,          desc="";
  RMW_Write,         desc="";
  Locked_RMW_Read,   desc="";
  Locked_RMW_Write,  desc="";
  COMMIT,            desc="Commit version";
  NULL,              desc="Invalid request type";
  FLUSH,             desc="Flush request type";
  Release,           desc="Release operation";
  Acquire,           desc="Acquire opertion";
  AcquireRelease,    desc="Acquire and Release opertion";
}

enumeration(SequencerRequestType, desc="...", default="SequencerRequestType_NULL") {
  Default,    desc="Replace this with access_types passed to the DMA Ruby object";
  LD,          desc="Load";
  ST,          desc="Store";
  NULL,        desc="Invalid request type";
}

enumeration(CacheRequestType, desc="...", default="CacheRequestType_NULL") {
  DataArrayRead,    desc="Read access to the cache's data array";
  DataArrayWrite,   desc="Write access to the cache's data array";
  TagArrayRead,     desc="Read access to the cache's tag array";
  TagArrayWrite,    desc="Write access to the cache's tag array";
}

enumeration(CacheResourceType, desc="...", default="CacheResourceType_NULL") {
  DataArray,    desc="Access to the cache's data array";
  TagArray,     desc="Access to the cache's tag array";
}

enumeration(DirectoryRequestType, desc="...", default="DirectoryRequestType_NULL") {
  Default,    desc="Replace this with access_types passed to the Directory Ruby object";
}

enumeration(DMASequencerRequestType, desc="...", default="DMASequencerRequestType_NULL") {
  Default,    desc="Replace this with access_types passed to the DMA Ruby object";
}

enumeration(MemoryControlRequestType, desc="...", default="MemoryControlRequestType_NULL") {
  Default,    desc="Replace this with access_types passed to the DMA Ruby object";
}

// MessageSizeType
enumeration(MessageSizeType, desc="...") {
  Control,    desc="Control Message";
  Data,       desc="Data Message";
  Request_Control, desc="Request";
  Reissue_Control, desc="Reissued request";
  Response_Data, desc="data response";
  ResponseL2hit_Data, desc="data response";
  ResponseLocal_Data, desc="data response";
  Response_Control, desc="non-data response";
  Writeback_Data, desc="Writeback data";
  Writeback_Control, desc="Writeback control";
  Broadcast_Control, desc="Broadcast control";
  Multicast_Control, desc="Multicast control";
  Forwarded_Control, desc="Forwarded control";
  Invalidate_Control, desc="Invalidate control";
  Unblock_Control, desc="Unblock control";
  Persistent_Control, desc="Persistent request activation messages";
  Completion_Control, desc="Completion messages";
}

// AccessType
enumeration(AccessType, desc="...") {
  Read, desc="Reading from cache";
  Write, desc="Writing to cache";
}

// RubyAccessMode
enumeration(RubyAccessMode, default="RubyAccessMode_User", desc="...") {
  Supervisor, desc="Supervisor mode";
  User,       desc="User mode";
  Device, desc="Device mode";
}

enumeration(PrefetchBit, default="PrefetchBit_No", desc="...") {
  No,    desc="No, not a prefetch";
  Yes,   desc="Yes, a prefetch";
  L1_HW, desc="This is a L1 hardware prefetch";
  L2_HW, desc="This is a L2 hardware prefetch";
}

// CacheMsg
structure(SequencerMsg, desc="...", interface="Message") {
  Address LineAddress,       desc="Line address for this request";
  Address PhysicalAddress,   desc="Physical address for this request";
  SequencerRequestType Type,     desc="Type of request (LD, ST, etc)";
  Address ProgramCounter,    desc="Program counter of the instruction that caused the miss";
  RubyAccessMode AccessMode, desc="user/supervisor access type";
  DataBlock DataBlk,         desc="Data";
  int Len,                   desc="size in bytes of access";
  PrefetchBit Prefetch,      desc="Is this a prefetch request";
  MessageSizeType MessageSize;

  bool functionalRead(Packet *pkt) {
    return testAndRead(PhysicalAddress, DataBlk, pkt);
  }

  bool functionalWrite(Packet *pkt) {
    return testAndWrite(PhysicalAddress, DataBlk, pkt);
  }
}

// MaskPredictorType
enumeration(MaskPredictorType, "MaskPredictorType_Undefined", desc="...") {
  Undefined, desc="Undefined";
  AlwaysUnicast, desc="AlwaysUnicast";
  TokenD, desc="TokenD";
  AlwaysBroadcast, desc="AlwaysBroadcast";
  TokenB, desc="TokenB";
  TokenNull, desc="TokenNull";
  Random, desc="Random";
  Pairwise, desc="Pairwise";
  Owner, desc="Owner";
  BroadcastIfShared, desc="Broadcast-If-Shared";
  BroadcastCounter, desc="Broadcast Counter";
  Group, desc="Group";
  Counter, desc="Counter";
  StickySpatial, desc="StickySpatial";
  OwnerBroadcast, desc="Owner/Broadcast Hybrid";
  OwnerGroup, desc="Owner/Group Hybrid";
  OwnerBroadcastMod, desc="Owner/Broadcast Hybrid-Mod";
  OwnerGroupMod, desc="Owner/Group Hybrid-Mod";
  LastNMasks, desc="Last N Masks";
  BandwidthAdaptive, desc="Bandwidth Adaptive";
}

// MaskPredictorIndex
enumeration(MaskPredictorIndex, "MaskPredictorIndex_Undefined", desc="...") {
  Undefined, desc="Undefined";
  DataBlock, desc="Data Block";
  PC, desc="Program Counter";
}

// MaskPredictorTraining
enumeration(MaskPredictorTraining, "MaskPredictorTraining_Undefined", desc="...") {
  Undefined, desc="Undefined";
  None, desc="None";
  Implicit, desc="Implicit";
  Explicit, desc="Explicit";
  Both, desc="Both";
}

// Request Status
enumeration(RequestStatus, desc="...", default="RequestStatus_NULL")  {
  Ready, desc="The sequencer is ready and the request does not alias";
  Issued, desc="The sequencer successfully issued the request";
  BufferFull, desc="Can not issue because the sequencer is full";
  Aliased, desc="This request aliased with a currently outstanding request";
  NULL, desc="";
}

// LinkDirection
enumeration(LinkDirection, desc="...") {
  In, desc="Inward link direction";
  Out, desc="Outward link direction";
}