summaryrefslogtreecommitdiff
path: root/src/mem/ruby/config/MOESI_CMP_directory.rb
blob: 936eb8e80c7cc10abc327164524a68dd27c7b874 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79

require "cfg.rb"

def log_int(n)
  assert(n.is_a?(Fixnum), "log_int takes a number for an argument")
  counter = 0
  while n >= 2 do
    counter += 1
    n = n >> 1
  end
  return counter
end


class MOESI_CMP_directory_L1CacheController < L1CacheController
  attr :icache, :dcache
  attr :num_l2_controllers
  def initialize(obj_name, mach_type, icache, dcache, sequencer, num_l2_controllers)
    super(obj_name, mach_type, [icache, dcache], sequencer)
    @icache = icache
    @dcache = dcache
    @num_l2_controllers = num_l2_controllers
  end
  def argv()
    num_select_bits = log_int(num_l2_controllers)
    num_block_bits = log_int(RubySystem.block_size_bytes)

    l2_select_low_bit = num_block_bits
    l2_select_high_bit = num_block_bits + num_select_bits - 1

    vec = super()
    vec += " icache " + @icache.obj_name
    vec += " dcache " + @dcache.obj_name
    vec += " request_latency "+request_latency().to_s
    vec += " l2_select_low_bit " + l2_select_low_bit.to_s
    vec += " l2_select_high_bit " + l2_select_high_bit.to_s
    return vec
  end
end

class MOESI_CMP_directory_L2CacheController < CacheController
  attr :cache
  def initialize(obj_name, mach_type, cache)
    super(obj_name, mach_type, [cache])
    @cache = cache
  end
  def argv()
    vec = super()
    vec += " cache " + @cache.obj_name
    vec += " request_latency "+request_latency().to_s
    vec += " response_latency "+response_latency().to_s
    return vec
  end
end


class MOESI_CMP_directory_DirectoryController < DirectoryController
  def initialize(obj_name, mach_type, directory, memory_control)
    super(obj_name, mach_type, directory, memory_control)
  end
  def argv()
    vec = super()
    vec += " directory_latency "+directory_latency.to_s
    return vec
  end

end

class MOESI_CMP_directory_DMAController < DMAController
  def initialize(obj_name, mach_type, dma_sequencer)
    super(obj_name, mach_type, dma_sequencer)
  end
  def argv()
    vec = super
    vec += " request_latency "+request_latency.to_s
    vec += " response_latency "+response_latency.to_s
    return vec
  end
end