summaryrefslogtreecommitdiff
path: root/src/mem/ruby/system/BankedArray.cc
blob: 3113393a16221b34ac3884831f7ea57e7a11bbf3 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57


#include <vector>

#include "base/intmath.hh"
#include "mem/ruby/common/TypeDefines.hh"
#include "mem/ruby/system/BankedArray.hh"
#include "sim/eventq.hh"

BankedArray::BankedArray(unsigned int banks, unsigned int accessLatency, unsigned int startIndexBit) :
    EventManager(&mainEventQueue)
{
    this->banks = banks;
    this->accessLatency = accessLatency;
    this->startIndexBit = startIndexBit;

    if (banks != 0) {
        bankBits = floorLog2(banks);
    }

    busyBanks.resize(banks);
}

bool
BankedArray::tryAccess(Index idx)
{
    if (accessLatency == 0)
        return true;

    unsigned int bank = mapIndexToBank(idx);
    assert(bank < banks);

    if (busyBanks[bank].scheduled()) {
        if (!(busyBanks[bank].startAccess == curTick() && busyBanks[bank].idx == idx)) {
            return false;
        } else {
            return true;  // We tried to allocate resources twice in the same cycle for the same addr
        }
    }

    busyBanks[bank].idx = idx;
    busyBanks[bank].startAccess = curTick();

    // substract 1 so that next cycle the resource available
    schedule(busyBanks[bank], curTick()+accessLatency-1);

    return true;
}

unsigned int
BankedArray::mapIndexToBank(Index idx)
{
    if (banks == 1) {
        return 0;
    }
    return idx % banks;
}