src/mem/ruby/system/BankedArray.hh


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47


#ifndef __MEM_RUBY_SYSTEM_BANKEDARRAY_HH__
#define __MEM_RUBY_SYSTEM_BANKEDARRAY_HH__

#include <vector>

#include "mem/ruby/common/TypeDefines.hh"
#include "sim/eventq.hh"


class BankedArray : public EventManager
{
private:
    unsigned int banks;
    unsigned int accessLatency;
    unsigned int bankBits;
    unsigned int startIndexBit;

    //std::vector<bool> busyBanks;

    class TickEvent : public Event
    {
    public:
        TickEvent() : Event() {}
        void process() {}
        Index idx;
        Tick startAccess;
    };
    friend class TickEvent;

    // If the tick event is scheduled then the bank is busy
    // otherwise, schedule the event and wait for it to complete
    std::vector<TickEvent> busyBanks;

    unsigned int mapIndexToBank(Index idx);

public:
    BankedArray(unsigned int banks, unsigned int accessLatency, unsigned int startIndexBit);

    // Note: We try the access based on the cache index, not the address
    // This is so we don't get aliasing on blocks being replaced
    bool tryAccess(Index idx);

};

#endif