blob: 12a5c790f92a02bee13ad5f1ba718acabf722789 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
|
#ifndef DMASEQUENCER_H
#define DMASEQUENCER_H
#include <ostream>
#include "mem/ruby/common/DataBlock.hh"
#include "mem/ruby/system/RubyPort.hh"
#include "params/DMASequencer.hh"
struct DMARequest {
uint64_t start_paddr;
int len;
bool write;
int bytes_completed;
int bytes_issued;
uint8* data;
int64_t id;
};
class DMASequencer :public RubyPort {
public:
typedef DMASequencerParams Params;
DMASequencer(const Params *);
void init();
/* external interface */
int64_t makeRequest(const RubyRequest & request);
bool isReady(const RubyRequest & request, bool dont_set = false) { assert(0); return false;};
// void issueRequest(uint64_t paddr, uint8* data, int len, bool rw);
bool busy() { return m_is_busy;}
/* SLICC callback */
void dataCallback(const DataBlock & dblk);
void ackCallback();
void printConfig(std::ostream & out);
private:
void issueNext();
private:
bool m_is_busy;
uint64_t m_data_block_mask;
DMARequest active_request;
int num_active_requests;
};
#endif // DMACONTROLLER_H
|
