1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
|
from m5.SimObject import SimObject
from m5.params import *
from m5.proxy import *
from m5 import build_env
from AlphaTLB import AlphaDTB, AlphaITB
from SparcTLB import SparcDTB, SparcITB
from Bus import Bus
import sys
class BaseCPU(SimObject):
type = 'BaseCPU'
abstract = True
system = Param.System(Parent.any, "system object")
cpu_id = Param.Int("CPU identifier")
if build_env['FULL_SYSTEM']:
if build_env['TARGET_ISA'] == 'sparc':
dtb = Param.SparcDTB(SparcDTB(), "Data TLB")
itb = Param.SparcITB(SparcITB(), "Instruction TLB")
elif build_env['TARGET_ISA'] == 'alpha':
dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB")
itb = Param.AlphaITB(AlphaITB(), "Instruction TLB")
else:
print "Unknown architecture, can't pick TLBs"
sys.exit(1)
else:
workload = VectorParam.Process("processes to run")
max_insts_all_threads = Param.Counter(0,
"terminate when all threads have reached this inst count")
max_insts_any_thread = Param.Counter(0,
"terminate when any thread reaches this inst count")
max_loads_all_threads = Param.Counter(0,
"terminate when all threads have reached this load count")
max_loads_any_thread = Param.Counter(0,
"terminate when any thread reaches this load count")
progress_interval = Param.Tick(0, "interval to print out the progress message")
defer_registration = Param.Bool(False,
"defer registration with system (for sampling)")
clock = Param.Clock(Parent.clock, "clock speed")
_mem_ports = []
def connectMemPorts(self, bus):
for p in self._mem_ports:
exec('self.%s = bus.port' % p)
def addPrivateSplitL1Caches(self, ic, dc):
assert(len(self._mem_ports) == 2)
self.icache = ic
self.dcache = dc
self.icache_port = ic.cpu_side
self.dcache_port = dc.cpu_side
self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
self.addPrivateSplitL1Caches(ic, dc)
self.toL2Bus = Bus()
self.connectMemPorts(self.toL2Bus)
self.l2cache = l2c
self.l2cache.cpu_side = self.toL2Bus.port
self._mem_ports = ['l2cache.mem_side']
|
