1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
|
/*****************************************************************************
Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
more contributor license agreements. See the NOTICE file distributed
with this work for additional information regarding copyright ownership.
Accellera licenses this file to you under the Apache License, Version 2.0
(the "License"); you may not use this file except in compliance with the
License. You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
implied. See the License for the specific language governing
permissions and limitations under the License.
*****************************************************************************/
/*****************************************************************************
tb.h --
Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
*****************************************************************************/
/*****************************************************************************
MODIFICATION LOG - modifiers, enter your name, affiliation, date and
changes you are making here.
Name, Affiliation, Date:
Description of Modification:
*****************************************************************************/
/* Common interface file for test bench
Author: PRP
*/
#include "systemc.h"
SC_MODULE( tb )
{
SC_HAS_PROCESS( tb );
sc_in_clk clk;
// Output Reset Port
sc_signal<bool>& reset_sig;
// Output Data Ports
sc_signal<int>& i1;
sc_signal<int>& i2;
sc_signal<int>& i3;
sc_signal<int>& i4;
sc_signal<int>& i5;
// Output Control Ports
sc_signal<bool>& cont1;
sc_signal<bool>& cont2;
sc_signal<bool>& cont3;
// Input Data Ports
const sc_signal<int>& o1;
const sc_signal<int>& o2;
const sc_signal<int>& o3;
const sc_signal<int>& o4;
const sc_signal<int>& o5;
// Constructor
tb (
sc_module_name NAME,
sc_clock& CLK,
sc_signal<bool>& RESET_SIG,
sc_signal<int>& I1,
sc_signal<int>& I2,
sc_signal<int>& I3,
sc_signal<int>& I4,
sc_signal<int>& I5,
sc_signal<bool>& CONT1,
sc_signal<bool>& CONT2,
sc_signal<bool>& CONT3,
const sc_signal<int>& O1,
const sc_signal<int>& O2,
const sc_signal<int>& O3,
const sc_signal<int>& O4,
const sc_signal<int>& O5)
: reset_sig(RESET_SIG), i1(I1), i2(I2),
i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2),
cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5)
{
clk(CLK);
SC_CTHREAD( entry, clk.pos() );
}
void entry();
};
|
