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|
---------- Begin Simulation Statistics ----------
sim_seconds 0.181677 # Number of seconds simulated
sim_ticks 181676511500 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 82416 # Simulator instruction rate (inst/s)
host_tick_rate 24857445 # Simulator tick rate (ticks/s)
host_mem_usage 257796 # Number of bytes of host memory used
host_seconds 7308.74 # Real time elapsed on the host
sim_insts 602359820 # Number of instructions simulated
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 48 # Number of system calls
system.cpu.numCycles 363353024 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 93642406 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 86055517 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 3937297 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 88612742 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 82226729 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 1811116 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 1799 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 80077128 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 720176236 # Number of instructions fetch has processed
system.cpu.fetch.Branches 93642406 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 84037845 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 163199656 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 20933611 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 102893232 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 623 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 77424762 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 1579270 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 362477887 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.126441 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.976296 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 199278398 54.98% 54.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 25830413 7.13% 62.10% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 19932307 5.50% 67.60% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 25118126 6.93% 74.53% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 12539166 3.46% 77.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 13666852 3.77% 81.76% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 4829528 1.33% 83.09% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 7994396 2.21% 85.30% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 53288701 14.70% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 362477887 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.257717 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.982029 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 102756406 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 83077250 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 141158544 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 19181042 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 16304645 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 6938686 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 2613 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 758024516 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 7262 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 16304645 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 116075491 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 10185612 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 109358 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 146924183 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 72878598 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 743558817 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 188 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 58921601 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 10117687 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 591 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 767454765 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 3458233737 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 3458233609 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 627417418 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 140037342 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 6399 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 6398 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 130096693 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 183828757 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 85345746 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 25811031 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 37497456 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 715547655 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 7366 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 667339389 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 840250 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 112563133 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 285197370 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 1065 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 362477887 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.841049 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.675765 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 89414922 24.67% 24.67% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 90190265 24.88% 49.55% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 79396670 21.90% 71.45% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 45359007 12.51% 83.97% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 28036434 7.73% 91.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 16328709 4.50% 96.21% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 8232346 2.27% 98.48% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 5060866 1.40% 99.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 458668 0.13% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 362477887 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 175813 5.16% 5.16% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 5.16% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 5.16% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.16% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.16% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.16% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 5.16% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.16% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 5.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 5.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.16% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 2586346 75.94% 81.11% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 643459 18.89% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 414934483 62.18% 62.18% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 6549 0.00% 62.18% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.18% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.18% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.18% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.18% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.18% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.18% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.18% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 174108289 26.09% 88.27% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 78290065 11.73% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 667339389 # Type of FU issued
system.cpu.iq.rate 1.836614 # Inst issue rate
system.cpu.iq.fu_busy_cnt 3405618 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.005103 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 1701402497 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 828782976 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 653330026 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 670744987 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 28288943 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 34876158 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 159827 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 665311 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 15124729 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 15440 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 12578 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 16304645 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 784511 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 50454 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 715624477 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 2065189 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 183828757 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 85345746 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 6034 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 13250 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 5066 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 665311 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 4094363 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 486296 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 4580659 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 659689382 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 170637671 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 7650007 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 69456 # number of nop insts executed
system.cpu.iew.exec_refs 247330517 # number of memory reference insts executed
system.cpu.iew.exec_branches 76920251 # Number of branches executed
system.cpu.iew.exec_stores 76692846 # Number of stores executed
system.cpu.iew.exec_rate 1.815560 # Inst execution rate
system.cpu.iew.wb_sent 655349780 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 653330042 # cumulative count of insts written-back
system.cpu.iew.wb_producers 425170180 # num instructions producing a value
system.cpu.iew.wb_consumers 661395893 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.798059 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.642838 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 602359871 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 113270616 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 6301 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 3996549 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 346173243 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.740053 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.116155 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 112054418 32.37% 32.37% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 109168598 31.54% 63.91% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 49782434 14.38% 78.29% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 10491888 3.03% 81.32% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 23443534 6.77% 88.09% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 14637280 4.23% 92.32% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 8029663 2.32% 94.64% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 1511197 0.44% 95.07% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 17054231 4.93% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 346173243 # Number of insts commited each cycle
system.cpu.commit.count 602359871 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 219173615 # Number of memory references committed
system.cpu.commit.loads 148952598 # Number of loads committed
system.cpu.commit.membars 1328 # Number of memory barriers committed
system.cpu.commit.branches 70828605 # Number of branches committed
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
system.cpu.commit.int_insts 533522655 # Number of committed integer instructions.
system.cpu.commit.function_calls 997573 # Number of function calls committed.
system.cpu.commit.bw_lim_events 17054231 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 1044748887 # The number of ROB reads
system.cpu.rob.rob_writes 1447602374 # The number of ROB writes
system.cpu.timesIdled 36933 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 875137 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 602359820 # Number of Instructions Simulated
system.cpu.committedInsts_total 602359820 # Number of Instructions Simulated
system.cpu.cpi 0.603216 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.603216 # CPI: Total CPI of All Threads
system.cpu.ipc 1.657781 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.657781 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 3292742614 # number of integer regfile reads
system.cpu.int_regfile_writes 679039343 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
system.cpu.misc_regfile_reads 961073357 # number of misc regfile reads
system.cpu.misc_regfile_writes 2664 # number of misc regfile writes
system.cpu.icache.replacements 52 # number of replacements
system.cpu.icache.tagsinuse 658.859257 # Cycle average of tags in use
system.cpu.icache.total_refs 77423742 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 777 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 99644.455598 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 658.859257 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.321709 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 77423742 # number of ReadReq hits
system.cpu.icache.demand_hits 77423742 # number of demand (read+write) hits
system.cpu.icache.overall_hits 77423742 # number of overall hits
system.cpu.icache.ReadReq_misses 1020 # number of ReadReq misses
system.cpu.icache.demand_misses 1020 # number of demand (read+write) misses
system.cpu.icache.overall_misses 1020 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 35800500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 35800500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 35800500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 77424762 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 77424762 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 77424762 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000013 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000013 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 35098.529412 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 35098.529412 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 35098.529412 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 243 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 243 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 243 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 777 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 777 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 777 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 26636000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 26636000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 26636000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000010 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000010 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34280.566281 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 34280.566281 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 34280.566281 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 440951 # number of replacements
system.cpu.dcache.tagsinuse 4094.785016 # Cycle average of tags in use
system.cpu.dcache.total_refs 208890975 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 445047 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 469.368348 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 87843000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4094.785016 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.999703 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 140815101 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 68073201 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 1342 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits 1331 # number of StoreCondReq hits
system.cpu.dcache.demand_hits 208888302 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 208888302 # number of overall hits
system.cpu.dcache.ReadReq_misses 248858 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 1344330 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses 9 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses 1593188 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 1593188 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 3280375500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 26109782527 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency 194000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency 29390158027 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 29390158027 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 141063959 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 69417531 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses 1351 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses 1331 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 210481490 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 210481490 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.001764 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.019366 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate 0.006662 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate 0.007569 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.007569 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 13181.716079 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 19422.152691 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency 21555.555556 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency 18447.388524 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 18447.388524 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 9583027 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 2185 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 4385.824714 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 395037 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 51168 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 1096973 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits 9 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits 1148141 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 1148141 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 197690 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 247357 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 445047 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 445047 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 1624799500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 2561111027 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 4185910527 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 4185910527 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001401 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.003563 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.002114 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.002114 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8218.926096 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10353.905598 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 9405.547115 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 9405.547115 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 72983 # number of replacements
system.cpu.l2cache.tagsinuse 17823.829612 # Cycle average of tags in use
system.cpu.l2cache.total_refs 421659 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 88508 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 4.764078 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 1903.131187 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 15920.698425 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.058079 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.485861 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 165659 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 395037 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 188979 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 354638 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 354638 # number of overall hits
system.cpu.l2cache.ReadReq_misses 32805 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 58381 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 91186 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 91186 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 1126836000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 2004580000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 3131416000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 3131416000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 198464 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 395037 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 247360 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 445824 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 445824 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.165294 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.236016 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.204534 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.204534 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34349.519890 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34336.171015 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34340.973395 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34340.973395 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 2057500 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 352 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5845.170455 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks 58139 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits 9 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits 9 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 9 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 32796 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 58381 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 91177 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 91177 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1020208500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1822855000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 2843063500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 2843063500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165249 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.236016 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.204513 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.204513 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31107.711306 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31223.428855 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31181.805719 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31181.805719 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
|
