blob: f737a8e3b706099f25b84a43fe6d61975a54e1dc (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
|
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
global.BPredUnit.BTBHits 183932235 # Number of BTB hits
global.BPredUnit.BTBLookups 208089812 # Number of BTB lookups
global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect 84447535 # Number of conditional branches incorrect
global.BPredUnit.condPredicted 256528366 # Number of conditional branches predicted
global.BPredUnit.lookups 256528366 # Number of BP lookups
global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
host_inst_rate 94020 # Simulator instruction rate (inst/s)
host_mem_usage 184848 # Number of bytes of host memory used
host_seconds 14950.16 # Real time elapsed on the host
host_tick_rate 73409017 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 458856790 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 141228058 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 745627925 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 302069201 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1405610550 # Number of instructions simulated
sim_seconds 1.097477 # Number of seconds simulated
sim_ticks 1097476890500 # Number of ticks simulated
system.cpu.commit.COM:branches 86246390 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 9005633 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle.samples 1955398373
system.cpu.commit.COM:committed_per_cycle.min_value 0
0 1080294174 5524.68%
1 576226777 2946.85%
2 118746551 607.28%
3 121516054 621.44%
4 26673737 136.41%
5 9328411 47.71%
6 9370387 47.92%
7 4236649 21.67%
8 9005633 46.06%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
system.cpu.commit.COM:count 1489528973 # Number of instructions committed
system.cpu.commit.COM:loads 402516086 # Number of loads committed
system.cpu.commit.COM:membars 51356 # Number of memory barriers committed
system.cpu.commit.COM:refs 569373868 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 84447535 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 1489528973 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 2243501 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 1399558822 # The number of squashed insts skipped by commit
system.cpu.committedInsts 1405610550 # Number of Instructions Simulated
system.cpu.committedInsts_total 1405610550 # Number of Instructions Simulated
system.cpu.cpi 1.561566 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.561566 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 422711094 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 22402.386533 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4523.374198 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 422473888 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 5313980500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000561 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 237206 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 708416 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 1072971500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000561 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 237206 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_avg_miss_latency 7025 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 5025 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits
system.cpu.dcache.SwapReq_miss_latency 281000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses
system.cpu.dcache.SwapReq_mshr_miss_latency 201000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses
system.cpu.dcache.WriteReq_accesses 165053813 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 45668.908621 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5916.368381 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 164707389 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 15820806000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.002099 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 346424 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 1802643 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 2049572000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.002099 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 346424 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 1145.843040 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 587764907 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 36212.645854 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 5350.210750 # average overall mshr miss latency
system.cpu.dcache.demand_hits 587181277 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 21134786500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000993 # miss rate for demand accesses
system.cpu.dcache.demand_misses 583630 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 2511059 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 3122543500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000993 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 583630 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 587764907 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 36212.645854 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 5350.210750 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 587181277 # number of overall hits
system.cpu.dcache.overall_miss_latency 21134786500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000993 # miss rate for overall accesses
system.cpu.dcache.overall_misses 583630 # number of overall misses
system.cpu.dcache.overall_mshr_hits 2511059 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 3122543500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000993 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 583630 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 508412 # number of replacements
system.cpu.dcache.sampled_refs 512508 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4095.762102 # Cycle average of tags in use
system.cpu.dcache.total_refs 587253725 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 80526000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 343259 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 406688141 # Number of cycles decode is blocked
system.cpu.decode.DECODE:DecodedInsts 3452580675 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 760521931 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 785512506 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 239555254 # Number of cycles decode is squashing
system.cpu.decode.DECODE:UnblockCycles 2675795 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 256528366 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 355016142 # Number of cache lines fetched
system.cpu.fetch.Cycles 1201036760 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 10894008 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 3738352844 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 89458561 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.116872 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 355016142 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 183932235 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.703158 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist.samples 2194953627
system.cpu.fetch.rateDist.min_value 0
0 1348933053 6145.61%
1 256313247 1167.74%
2 82698191 376.77%
3 38326183 174.61%
4 84519360 385.06%
5 41105906 187.27%
6 32923583 150.00%
7 20556634 93.65%
8 289577470 1319.29%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
system.cpu.icache.ReadReq_accesses 355016079 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 7452.363368 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 5292.836041 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 355014725 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 10090500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 1354 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 63 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 7166500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 1354 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 262196.990399 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 355016079 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 7452.363368 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 5292.836041 # average overall mshr miss latency
system.cpu.icache.demand_hits 355014725 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 10090500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
system.cpu.icache.demand_misses 1354 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 63 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 7166500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 1354 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 355016079 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 7452.363368 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 5292.836041 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 355014725 # number of overall hits
system.cpu.icache.overall_miss_latency 10090500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
system.cpu.icache.overall_misses 1354 # number of overall misses
system.cpu.icache.overall_mshr_hits 63 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 7166500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 1354 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 208 # number of replacements
system.cpu.icache.sampled_refs 1354 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1042.348080 # Cycle average of tags in use
system.cpu.icache.total_refs 355014725 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 94965 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 128778452 # Number of branches executed
system.cpu.iew.EXEC:nop 354384689 # number of nop insts executed
system.cpu.iew.EXEC:rate 0.865881 # Inst execution rate
system.cpu.iew.EXEC:refs 753461994 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 210026063 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 1497813793 # num instructions consuming a value
system.cpu.iew.WB:count 1867109874 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.963032 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 1442442170 # num instructions producing a value
system.cpu.iew.WB:rate 0.850638 # insts written-back per cycle
system.cpu.iew.WB:sent 1877161076 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 91327681 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 454443 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 745627925 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 21367021 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 17089542 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 302069201 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 2889153048 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 543435931 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 103575555 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 1900567912 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 61243 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 9772 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 239555254 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 95884 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 119997179 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 80650 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 5250080 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 6 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 343111839 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 135211419 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 5250080 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 1516982 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 89810699 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 0.640383 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.640383 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 2004143467 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
No_OpClass 0 0.00% # Type of FU issued
IntAlu 1186366605 59.20% # Type of FU issued
IntMult 0 0.00% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 3003253 0.15% # Type of FU issued
FloatCmp 0 0.00% # Type of FU issued
FloatCvt 0 0.00% # Type of FU issued
FloatMult 0 0.00% # Type of FU issued
FloatDiv 0 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
MemRead 584611723 29.17% # Type of FU issued
MemWrite 230161886 11.48% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
system.cpu.iq.ISSUE:fu_busy_cnt 6010355 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.002999 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
No_OpClass 0 0.00% # attempts to use FU when none available
IntAlu 143340 2.38% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 241345 4.02% # attempts to use FU when none available
FloatCmp 0 0.00% # attempts to use FU when none available
FloatCvt 0 0.00% # attempts to use FU when none available
FloatMult 0 0.00% # attempts to use FU when none available
FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
MemRead 5244225 87.25% # attempts to use FU when none available
MemWrite 381445 6.35% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle.samples 2194953627
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
0 1076765226 4905.64%
1 582878371 2655.54%
2 298125643 1358.23%
3 159003575 724.41%
4 52530250 239.32%
5 16707223 76.12%
6 8404252 38.29%
7 392238 1.79%
8 146849 0.67%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
system.cpu.iq.ISSUE:rate 0.913069 # Inst issue rate
system.cpu.iq.iqInstsAdded 2513084593 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 2004143467 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 21683766 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 1087893079 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 3817087 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 19440265 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 1299740082 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadExReq_accesses 275303 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 4888.651776 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2888.651776 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 1345860500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 275303 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 795254500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 275303 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 238559 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 4206.099871 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2206.099871 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 56424 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 766078000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.763480 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 182135 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 401808000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.763480 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 182135 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 71169 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 4205.419494 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2205.419494 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 299295500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 71169 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 156957500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 71169 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 343259 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses
system.cpu.l2cache.Writeback_misses 343259 # number of Writeback misses
system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
system.cpu.l2cache.Writeback_mshr_misses 343259 # number of Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 4.652891 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 513862 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 4616.884693 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 2616.884693 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 56424 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 2111938500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.890196 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 457438 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 1197062500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.890196 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 457438 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 513862 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 4616.884693 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 2616.884693 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 56424 # number of overall hits
system.cpu.l2cache.overall_miss_latency 2111938500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.890196 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 457438 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 1197062500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.890196 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 457438 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 19390 # number of replacements
system.cpu.l2cache.sampled_refs 20786 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 8527.413561 # Cycle average of tags in use
system.cpu.l2cache.total_refs 96715 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.numCycles 2194953627 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 13000888 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 1244771057 # Number of HB maps that are committed
system.cpu.rename.RENAME:FullRegisterEvents 9 # Number of times there has been no free registers
system.cpu.rename.RENAME:IQFullEvents 47407 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 822770114 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 20101500 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 4935577703 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 3109070263 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 2428488542 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 723045080 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 239555254 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 28402170 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 1183717485 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 368180121 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 21968418 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 159248004 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 21723083 # count of temporary serializing insts renamed
system.cpu.timesIdled 35 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 19 # Number of system calls
---------- End Simulation Statistics ----------
|
