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|
---------- Begin Simulation Statistics ----------
host_inst_rate 144426 # Simulator instruction rate (inst/s)
host_mem_usage 207996 # Number of bytes of host memory used
host_seconds 9732.45 # Real time elapsed on the host
host_tick_rate 61799305 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1405604152 # Number of instructions simulated
sim_seconds 0.601459 # Number of seconds simulated
sim_ticks 601458924000 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 98804590 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 100538418 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 5348296 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 105813144 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 105813144 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 86248929 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 21328117 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 1172142071 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.270770 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 1.680117 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 418029830 35.66% 35.66% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 498322942 42.51% 78.18% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 52997650 4.52% 82.70% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 103674512 8.84% 91.54% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 32914783 2.81% 94.35% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 8294110 0.71% 95.06% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 25633990 2.19% 97.25% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 10946137 0.93% 98.18% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 21328117 1.82% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 1172142071 # Number of insts commited each cycle
system.cpu.commit.COM:count 1489523295 # Number of instructions committed
system.cpu.commit.COM:loads 402512844 # Number of loads committed
system.cpu.commit.COM:membars 51356 # Number of memory barriers committed
system.cpu.commit.COM:refs 569360986 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 5348296 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 1489523295 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 219357232 # The number of squashed insts skipped by commit
system.cpu.committedInsts 1405604152 # Number of Instructions Simulated
system.cpu.committedInsts_total 1405604152 # Number of Instructions Simulated
system.cpu.cpi 0.855801 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.855801 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 295701881 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 14657.940821 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7465.771391 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 294883584 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 11994549000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.002767 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 818297 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 604806 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 1593875000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000722 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 213491 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_avg_miss_latency 38142.857143 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35142.857143 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_hits 1319 # number of SwapReq hits
system.cpu.dcache.SwapReq_miss_latency 267000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_rate 0.005279 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_misses 7 # number of SwapReq misses
system.cpu.dcache.SwapReq_mshr_miss_latency 246000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses
system.cpu.dcache.WriteReq_accesses 166846816 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 15553.543798 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12825.966833 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 165080859 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 27466889545 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.010584 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1765957 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 1497892 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 3438192799 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.001607 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 268065 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 955.151791 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 462548697 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 15269.953551 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 10449.600460 # average overall mshr miss latency
system.cpu.dcache.demand_hits 459964443 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 39461438545 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.005587 # miss rate for demand accesses
system.cpu.dcache.demand_misses 2584254 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 2102698 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 5032067799 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.001041 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 481556 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.999859 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4095.424247 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 462548697 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 15269.953551 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 10449.600460 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 459964443 # number of overall hits
system.cpu.dcache.overall_miss_latency 39461438545 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.005587 # miss rate for overall accesses
system.cpu.dcache.overall_misses 2584254 # number of overall misses
system.cpu.dcache.overall_mshr_hits 2102698 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 5032067799 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.001041 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 481556 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 477467 # number of replacements
system.cpu.dcache.sampled_refs 481563 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4095.424247 # Cycle average of tags in use
system.cpu.dcache.total_refs 459965762 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 132304000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 428418 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 393633604 # Number of cycles decode is blocked
system.cpu.decode.DECODE:DecodedInsts 1750740297 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 405697462 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 351107020 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 30410517 # Number of cycles decode is squashing
system.cpu.decode.DECODE:UnblockCycles 21703374 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 105813144 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 173097327 # Number of cache lines fetched
system.cpu.fetch.Cycles 375137003 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 1429156 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 1755978912 # Number of instructions fetch has processed
system.cpu.fetch.MiscStallCycles 47 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.SquashCycles 6170643 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.087964 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 173097327 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 98804590 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.459766 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 1202551977 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.463999 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.699994 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 827414974 68.80% 68.80% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 82887161 6.89% 75.70% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 45821959 3.81% 79.51% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 22740624 1.89% 81.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 33832197 2.81% 84.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 32823900 2.73% 86.94% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 14990247 1.25% 88.19% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 7935660 0.66% 88.85% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 134105255 11.15% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1202551977 # Number of instructions fetched each cycle (Total)
system.cpu.icache.ReadReq_accesses 173097327 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 35070.194986 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35059.073359 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 173095532 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 62951000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 1795 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 500 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 45401500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000007 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 1295 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 133767.799073 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 173097327 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 35070.194986 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 35059.073359 # average overall mshr miss latency
system.cpu.icache.demand_hits 173095532 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 62951000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000010 # miss rate for demand accesses
system.cpu.icache.demand_misses 1795 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 500 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 45401500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000007 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 1295 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.509893 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1044.260820 # Average occupied blocks per context
system.cpu.icache.overall_accesses 173097327 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 35070.194986 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35059.073359 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 173095532 # number of overall hits
system.cpu.icache.overall_miss_latency 62951000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000010 # miss rate for overall accesses
system.cpu.icache.overall_misses 1795 # number of overall misses
system.cpu.icache.overall_mshr_hits 500 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 45401500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000007 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 1295 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 158 # number of replacements
system.cpu.icache.sampled_refs 1294 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1044.260820 # Cycle average of tags in use
system.cpu.icache.total_refs 173095532 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 365872 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 89387996 # Number of branches executed
system.cpu.iew.EXEC:nop 102270134 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.226826 # Inst execution rate
system.cpu.iew.EXEC:refs 590482875 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 169844843 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 1212153101 # num instructions consuming a value
system.cpu.iew.WB:count 1472498717 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.958322 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 1161632680 # num instructions producing a value
system.cpu.iew.WB:rate 1.224106 # insts written-back per cycle
system.cpu.iew.WB:sent 1473870381 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 5524543 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 2523096 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 468104279 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 2975263 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 4542154 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 188276128 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 1708972338 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 420638032 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 6157621 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 1475771230 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 66958 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 9816 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 30410517 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 130917 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 40442 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 124904328 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 7473 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 832421 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 264 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 65591435 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 21427986 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 832421 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 648481 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 4876062 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.168496 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.168496 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 884685423 59.70% 59.70% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 59.70% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 59.70% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2618241 0.18% 59.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 59.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 59.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 59.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 59.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 59.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 59.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 59.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 59.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 59.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 59.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 59.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 59.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 59.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 59.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 59.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 59.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 59.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 59.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 59.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 59.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 59.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 59.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 59.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 59.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 59.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 423844959 28.60% 88.48% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 170780228 11.52% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total 1481928851 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 3245613 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.002190 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 213200 6.57% 6.57% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 6.57% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 6.57% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 176489 5.44% 12.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 12.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 12.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 12.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 12.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 12.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 12.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 12.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 12.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 12.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 12.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 12.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 12.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 12.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 12.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 12.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 12.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 12.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 12.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 12.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 12.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 12.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 12.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 12.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 12.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 12.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 2530154 77.96% 89.96% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 325770 10.04% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples 1202551977 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.232320 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.127764 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 320557298 26.66% 26.66% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 511598029 42.54% 69.20% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 219313490 18.24% 87.44% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 94900060 7.89% 95.33% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 39948235 3.32% 98.65% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 10701841 0.89% 99.54% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 5167806 0.43% 99.97% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 227063 0.02% 99.99% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 138155 0.01% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 1202551977 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.231945 # Inst issue rate
system.cpu.iq.iqInstsAdded 1603626285 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 1481928851 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 3075919 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 200593512 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 68539 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 832248 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 279087097 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadExReq_accesses 268080 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34407.350752 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31318.935009 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 207610 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 2080612500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.225567 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 60470 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1893856000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.225567 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 60470 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 214778 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34037.381235 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.958432 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 181098 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1146379000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.156813 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 33680 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1044247000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.156813 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 33680 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 428418 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 428418 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 5.114449 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 482858 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34275.002655 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31206.617100 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 388708 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 3226991500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.194985 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 94150 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 2938103000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.194985 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 94150 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.060606 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.478382 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 1985.934249 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 15675.618246 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 482858 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34275.002655 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31206.617100 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 388708 # number of overall hits
system.cpu.l2cache.overall_miss_latency 3226991500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.194985 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 94150 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 2938103000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.194985 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 94150 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 75917 # number of replacements
system.cpu.l2cache.sampled_refs 91429 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 17661.552495 # Cycle average of tags in use
system.cpu.l2cache.total_refs 467609 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 59275 # number of writebacks
system.cpu.memDep0.conflictingLoads 406523724 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 165663867 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 468104279 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 188276128 # Number of stores inserted to the mem dependence unit.
system.cpu.numCycles 1202917849 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 123850519 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 1244770452 # Number of HB maps that are committed
system.cpu.rename.RENAME:FullRegisterEvents 28358883 # Number of times there has been no free registers
system.cpu.rename.RENAME:IQFullEvents 134234465 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 443700933 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 41034559 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 3 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 2924501033 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 1732030714 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 1445194568 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 329588798 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 30410517 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 217220436 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 200424116 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 57780774 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 3037077 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 385267398 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 3036332 # count of temporary serializing insts renamed
system.cpu.timesIdled 11390 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 49 # Number of system calls
---------- End Simulation Statistics ----------
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