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---------- Begin Simulation Statistics ----------
host_inst_rate 531377 # Simulator instruction rate (inst/s)
host_mem_usage 154376 # Number of bytes of host memory used
host_seconds 2803.12 # Real time elapsed on the host
host_tick_rate 1212716 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1489514860 # Number of instructions simulated
sim_seconds 0.003399 # Number of seconds simulated
sim_ticks 3399390003 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 402511688 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 2848.782706 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 1848.782706 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 402318208 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 551182478 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000481 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 193480 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 357702478 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000481 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 193480 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_avg_miss_latency 3103.285714 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2103.285714 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_hits 1319 # number of SwapReq hits
system.cpu.dcache.SwapReq_miss_latency 21723 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_rate 0.005279 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_misses 7 # number of SwapReq misses
system.cpu.dcache.SwapReq_mshr_miss_latency 14723 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses
system.cpu.dcache.WriteReq_accesses 166846642 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 3023.717816 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2023.717816 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 166586897 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 785395584 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.001557 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 259745 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 525650584 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.001557 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 259745 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 1255.221220 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 569358330 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 2949.038694 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 1949.038694 # average overall mshr miss latency
system.cpu.dcache.demand_hits 568905105 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 1336578062 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000796 # miss rate for demand accesses
system.cpu.dcache.demand_misses 453225 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 883353062 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000796 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 453225 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 569358330 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 2949.038694 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 1949.038694 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 568905105 # number of overall hits
system.cpu.dcache.overall_miss_latency 1336578062 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000796 # miss rate for overall accesses
system.cpu.dcache.overall_misses 453225 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 883353062 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000796 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 453225 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 449136 # number of replacements
system.cpu.dcache.sampled_refs 453232 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4068.114109 # Cycle average of tags in use
system.cpu.dcache.total_refs 568906424 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 33495000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 316447 # number of writebacks
system.cpu.icache.ReadReq_accesses 1489514861 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 3979.992714 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2979.992714 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 1489513763 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 4370032 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 1098 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 3272032 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 1098 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 1356569.911658 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 1489514861 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 3979.992714 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 2979.992714 # average overall mshr miss latency
system.cpu.icache.demand_hits 1489513763 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 4370032 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
system.cpu.icache.demand_misses 1098 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 3272032 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 1098 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 1489514861 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 3979.992714 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 2979.992714 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 1489513763 # number of overall hits
system.cpu.icache.overall_miss_latency 4370032 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
system.cpu.icache.overall_misses 1098 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 3272032 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 1098 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 115 # number of replacements
system.cpu.icache.sampled_refs 1098 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 865.251814 # Cycle average of tags in use
system.cpu.icache.total_refs 1489513763 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadReq_accesses 454330 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 3215.864263 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1941.261615 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 427145 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 87423270 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.059835 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 27185 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 52773197 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.059835 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 27185 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 316447 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 316438 # number of Writeback hits
system.cpu.l2cache.Writeback_miss_rate 0.000028 # miss rate for Writeback accesses
system.cpu.l2cache.Writeback_misses 9 # number of Writeback misses
system.cpu.l2cache.Writeback_mshr_miss_rate 0.000028 # mshr miss rate for Writeback accesses
system.cpu.l2cache.Writeback_mshr_misses 9 # number of Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 27.352695 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 454330 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 3215.864263 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 1941.261615 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 427145 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 87423270 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.059835 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 27185 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 52773197 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.059835 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 27185 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 770777 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 3214.799956 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 1941.261615 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 743583 # number of overall hits
system.cpu.l2cache.overall_miss_latency 87423270 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.035281 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 27194 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 52773197 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.035270 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 27185 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 2632 # number of replacements
system.cpu.l2cache.sampled_refs 27185 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 23773.580402 # Cycle average of tags in use
system.cpu.l2cache.total_refs 743583 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 2531 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 3399390003 # number of cpu cycles simulated
system.cpu.num_insts 1489514860 # Number of instructions executed
system.cpu.num_refs 569359656 # Number of memory references
system.cpu.workload.PROG:num_syscalls 19 # Number of system calls
---------- End Simulation Statistics ----------
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