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---------- Begin Simulation Statistics ----------
host_inst_rate                                 751612                       # Simulator instruction rate (inst/s)
host_mem_usage                                 204588                       # Number of bytes of host memory used
host_seconds                                  2154.53                       # Real time elapsed on the host
host_tick_rate                             1185451424                       # Simulator tick rate (ticks/s)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                  1619365942                       # Number of instructions simulated
sim_seconds                                  2.554085                       # Number of seconds simulated
sim_ticks                                2554084828000                       # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses          418962758                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 21035.291697                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18035.291697                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits              418768378                       # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency     4088840000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate          0.000464                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses               194380                       # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency   3505700000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate     0.000464                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses          194380                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses         188186056                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency        56000                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency        53000                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits             187874337                       # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency   17456264000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate         0.001656                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses              311719                       # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency  16521107000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate     0.001656                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses         311719                       # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu.dcache.avg_refs                1367.059283                       # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs                  0                       # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets                0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.demand_accesses           607148814                       # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 42570.927822                       # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 39570.927822                       # average overall mshr miss latency
system.cpu.dcache.demand_hits               606642715                       # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency     21545104000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate           0.000834                       # miss rate for demand accesses
system.cpu.dcache.demand_misses                506099                       # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency  20026807000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate      0.000834                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses           506099                       # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses          607148814                       # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 42570.927822                       # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 39570.927822                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits              606642715                       # number of overall hits
system.cpu.dcache.overall_miss_latency    21545104000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_rate          0.000834                       # miss rate for overall accesses
system.cpu.dcache.overall_misses               506099                       # number of overall misses
system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency  20026807000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate     0.000834                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses          506099                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements                 439707                       # number of replacements
system.cpu.dcache.sampled_refs                 443803                       # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse               4094.610676                       # Cycle average of tags in use
system.cpu.dcache.total_refs                606705011                       # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle             1592465000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks                   308507                       # number of writebacks
system.cpu.icache.ReadReq_accesses         1925857355                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency        56000                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency        53000                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits             1925856634                       # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency       40376000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate          0.000000                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses                  721                       # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency     38213000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate     0.000000                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses             721                       # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu.icache.avg_refs               2671091.031900                       # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs                  0                       # number of cycles access was blocked
system.cpu.icache.blocked_no_targets                0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.demand_accesses          1925857355                       # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency        56000                       # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
system.cpu.icache.demand_hits              1925856634                       # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency        40376000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate           0.000000                       # miss rate for demand accesses
system.cpu.icache.demand_misses                   721                       # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency     38213000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate      0.000000                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses              721                       # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.overall_accesses         1925857355                       # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency        56000                       # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu.icache.overall_hits             1925856634                       # number of overall hits
system.cpu.icache.overall_miss_latency       40376000                       # number of overall miss cycles
system.cpu.icache.overall_miss_rate          0.000000                       # miss rate for overall accesses
system.cpu.icache.overall_misses                  721                       # number of overall misses
system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency     38213000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate     0.000000                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses             721                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.icache.replacements                      4                       # number of replacements
system.cpu.icache.sampled_refs                    721                       # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse                658.724808                       # Cycle average of tags in use
system.cpu.icache.total_refs               1925856634                       # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks                        0                       # number of writebacks
system.cpu.idle_fraction                            0                       # Percentage of idle cycles
system.cpu.l2cache.ReadExReq_accesses          249423                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency  12969996000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses            249423                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency   9976920000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses       249423                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses            195101                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits                161820                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency    1730612000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate         0.170583                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses               33281                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency   1331240000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate     0.170583                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses          33281                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses          62296                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency        52000                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        40000                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency   3239392000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses            62296                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency   2491840000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses        62296                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses          308507                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits              308507                       # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs                  3.404798                       # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs                 0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets               0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.demand_accesses             444524                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
system.cpu.l2cache.demand_hits                 161820                       # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency    14700608000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate          0.635970                       # miss rate for demand accesses
system.cpu.l2cache.demand_misses               282704                       # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency  11308160000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate     0.635970                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses          282704                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses            444524                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits                161820                       # number of overall hits
system.cpu.l2cache.overall_miss_latency   14700608000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate         0.635970                       # miss rate for overall accesses
system.cpu.l2cache.overall_misses              282704                       # number of overall misses
system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency  11308160000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate     0.635970                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses         282704                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements                 82097                       # number of replacements
system.cpu.l2cache.sampled_refs                 97587                       # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse             16428.009263                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                  332264                       # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks                   61702                       # number of writebacks
system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
system.cpu.numCycles                       5108169656                       # number of cpu cycles simulated
system.cpu.num_insts                       1619365942                       # Number of instructions executed
system.cpu.num_refs                         607148814                       # Number of memory references
system.cpu.workload.PROG:num_syscalls              48                       # Number of system calls

---------- End Simulation Statistics   ----------