path: root/tests/long/10.linux-boot/ref/alpha/linux/tsunami-inorder/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.899195                       # Number of seconds simulated
sim_ticks                                1899194993500                       # Number of ticks simulated
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 102570                       # Simulator instruction rate (inst/s)
host_tick_rate                             2450099766                       # Simulator tick rate (ticks/s)
host_mem_usage                                 278932                       # Number of bytes of host memory used
host_seconds                                   775.15                       # Real time elapsed on the host
sim_insts                                    79507003                       # Number of instructions simulated
system.l2c.replacements                        389890                       # number of replacements
system.l2c.tagsinuse                     34369.845754                       # Cycle average of tags in use
system.l2c.total_refs                         2354607                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        422592                       # Sample count of references to valid blocks.
system.l2c.avg_refs                          5.571821                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                    5902814000                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::0                 11156.941025                       # Average occupied blocks per context
system.l2c.occ_blocks::1                 23212.904730                       # Average occupied blocks per context
system.l2c.occ_percent::0                    0.170241                       # Average percentage of cache occupancy
system.l2c.occ_percent::1                    0.354201                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::0                    1754804                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1754804                       # number of ReadReq hits
system.l2c.Writeback_hits::0                   825539                       # number of Writeback hits
system.l2c.Writeback_hits::total               825539                       # number of Writeback hits
system.l2c.UpgradeReq_hits::0                       7                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                   7                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::0                   188732                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               188732                       # number of ReadExReq hits
system.l2c.demand_hits::0                     1943536                       # number of demand (read+write) hits
system.l2c.demand_hits::1                           0                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1943536                       # number of demand (read+write) hits
system.l2c.overall_hits::0                    1943536                       # number of overall hits
system.l2c.overall_hits::1                          0                       # number of overall hits
system.l2c.overall_hits::total                1943536                       # number of overall hits
system.l2c.ReadReq_misses::0                   304763                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               304763                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::0                     7                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total                 7                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::0                 118469                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             118469                       # number of ReadExReq misses
system.l2c.demand_misses::0                    423232                       # number of demand (read+write) misses
system.l2c.demand_misses::1                         0                       # number of demand (read+write) misses
system.l2c.demand_misses::total                423232                       # number of demand (read+write) misses
system.l2c.overall_misses::0                   423232                       # number of overall misses
system.l2c.overall_misses::1                        0                       # number of overall misses
system.l2c.overall_misses::total               423232                       # number of overall misses
system.l2c.ReadReq_miss_latency           15864418500                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency             249000                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency          6171282500                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency            22035701000                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency           22035701000                       # number of overall miss cycles
system.l2c.ReadReq_accesses::0                2059567                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2059567                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::0               825539                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           825539                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::0                  14                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total              14                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::0               307201                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           307201                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::0                 2366768                       # number of demand (read+write) accesses
system.l2c.demand_accesses::1                       0                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2366768                       # number of demand (read+write) accesses
system.l2c.overall_accesses::0                2366768                       # number of overall (read+write) accesses
system.l2c.overall_accesses::1                      0                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2366768                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::0              0.147974                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::0           0.500000                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::0            0.385640                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::0               0.178823                       # miss rate for demand accesses
system.l2c.demand_miss_rate::1               no_value                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           no_value                       # miss rate for demand accesses
system.l2c.overall_miss_rate::0              0.178823                       # miss rate for overall accesses
system.l2c.overall_miss_rate::1              no_value                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          no_value                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::0   52054.936131                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::1            inf                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::0 35571.428571                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::1          inf                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::0 52091.960766                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::1          inf                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::0    52065.299883                       # average overall miss latency
system.l2c.demand_avg_miss_latency::1             inf                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.l2c.overall_avg_miss_latency::0   52065.299883                       # average overall miss latency
system.l2c.overall_avg_miss_latency::1            inf                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks                          116891                       # number of writebacks
system.l2c.demand_mshr_hits                         0                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits                        0                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses                 304763                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses                   7                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses               118469                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses                  423232                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses                 423232                       # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency      12196601000                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency        321000                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency     4740688000                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency       16937289000                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency      16937289000                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency    811651000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency   1119429000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency   1931080000                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::0         0.147974                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::1              inf                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::0      0.500000                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::1           inf                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::0       0.385640                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::1            inf                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::0          0.178823                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::1               inf                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total           inf                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::0         0.178823                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::1              inf                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency 40019.953210                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency 45857.142857                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency 40016.274300                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency  40018.923427                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency 40018.923427                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.iocache.replacements                     41685                       # number of replacements
system.iocache.tagsinuse                     1.305719                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                     41701                       # Sample count of references to valid blocks.
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.warmup_cycle              1740606093000                       # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::1                 1.305719                       # Average occupied blocks per context
system.iocache.occ_percent::1                0.081607                       # Average percentage of cache occupancy
system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
system.iocache.overall_hits::0                      0                       # number of overall hits
system.iocache.overall_hits::1                      0                       # number of overall hits
system.iocache.overall_hits::total                  0                       # number of overall hits
system.iocache.ReadReq_misses::1                  173                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
system.iocache.WriteReq_misses::1               41552                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
system.iocache.demand_misses::1                 41725                       # number of demand (read+write) misses
system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
system.iocache.overall_misses::0                    0                       # number of overall misses
system.iocache.overall_misses::1                41725                       # number of overall misses
system.iocache.overall_misses::total            41725                       # number of overall misses
system.iocache.ReadReq_miss_latency          19963998                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency       5720707806                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency         5740671804                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency        5740671804                       # number of overall miss cycles
system.iocache.ReadReq_accesses::1                173                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::1             41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
system.iocache.demand_accesses::1               41725                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           41725                       # number of demand (read+write) accesses
system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
system.iocache.overall_accesses::1              41725                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::1                 1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::1                1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
system.iocache.demand_miss_rate::1                  1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
system.iocache.overall_miss_rate::1                 1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::1 115398.832370                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::0          inf                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::1 137675.871342                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::0          inf                       # average overall miss latency
system.iocache.demand_avg_miss_latency::1 137583.506387                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.iocache.overall_avg_miss_latency::0          inf                       # average overall miss latency
system.iocache.overall_avg_miss_latency::1 137583.506387                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs      64617964                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                10476                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs  6168.190531                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks                       41512                       # number of writebacks
system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
system.iocache.ReadReq_mshr_misses                173                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses             41552                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses               41725                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses              41725                       # number of overall MSHR misses
system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.iocache.ReadReq_mshr_miss_latency     10967998                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency   3559854894                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency    3570822892                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency   3570822892                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::1            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::0          inf                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::1            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::0           inf                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::1             1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::1            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency 63398.832370                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency 85672.287591                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency 85579.937496                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency 85579.937496                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                     12031830                       # DTB read hits
system.cpu.dtb.read_misses                      10329                       # DTB read misses
system.cpu.dtb.read_acv                           210                       # DTB read access violations
system.cpu.dtb.read_accesses                   728887                       # DTB read accesses
system.cpu.dtb.write_hits                     6468534                       # DTB write hits
system.cpu.dtb.write_misses                      1142                       # DTB write misses
system.cpu.dtb.write_acv                          157                       # DTB write access violations
system.cpu.dtb.write_accesses                  292164                       # DTB write accesses
system.cpu.dtb.data_hits                     18500364                       # DTB hits
system.cpu.dtb.data_misses                      11471                       # DTB misses
system.cpu.dtb.data_acv                           367                       # DTB access violations
system.cpu.dtb.data_accesses                  1021051                       # DTB accesses
system.cpu.itb.fetch_hits                      773687                       # ITB hits
system.cpu.itb.fetch_misses                      9100                       # ITB misses
system.cpu.itb.fetch_acv                          713                       # ITB acv
system.cpu.itb.fetch_accesses                  782787                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.numCycles                       3798914951                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.contextSwitches                       6446                       # Number of context switches
system.cpu.threadCycles                     133331613                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled                         2296368                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                      3687762143                       # Number of cycles cpu's stages were not processed
system.cpu.runCycles                        111152808                       # Number of cycles cpu stages are processed.
system.cpu.activity                          2.925909                       # Percentage of cycles cpu is active
system.cpu.comLoads                          12027889                       # Number of Load instructions committed
system.cpu.comStores                          6376597                       # Number of Store instructions committed
system.cpu.comBranches                       15426722                       # Number of Branches instructions committed
system.cpu.comNops                            6123598                       # Number of Nop instructions committed
system.cpu.comNonSpec                           20710                       # Number of Non-Speculative instructions committed
system.cpu.comInts                           39260671                       # Number of Integer instructions committed
system.cpu.comFloats                            29243                       # Number of Floating Point instructions committed
system.cpu.committedInsts                    79507003                       # Number of Instructions Simulated (Per-Thread)
system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions Simulated (Per-Thread)
system.cpu.committedInsts_total              79507003                       # Number of Instructions Simulated (Total)
system.cpu.cpi                              47.780885                       # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi                           no_value                       # CPI: Total SMT-CPI
system.cpu.cpi_total                        47.780885                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.020929                       # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc                           no_value                       # IPC: Total SMT-IPC
system.cpu.ipc_total                         0.020929                       # IPC: Total IPC of All Threads
system.cpu.branch_predictor.lookups          17886857                       # Number of BP lookups
system.cpu.branch_predictor.condPredicted     15450279                       # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect     12067312                       # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups       16082928                       # Number of BTB lookups
system.cpu.branch_predictor.BTBHits          11760845                       # Number of BTB hits
system.cpu.branch_predictor.usedRAS            748072                       # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect          698                       # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct       73.126268                       # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken     12717384                       # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken      5169473                       # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads     66085429                       # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites     51239825                       # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses    117325254                       # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads       156392                       # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites       166486                       # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses       322878                       # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards       23151020                       # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens                   18525347                       # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect     11562750                       # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect       483435                       # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted       12046185                       # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted           3381472                       # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct     78.081753                       # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions         55021479                       # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies             60941                       # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
system.cpu.stage0.idleCycles               3695693335                       # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles                 103221616                       # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization                2.717134                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles               3723812456                       # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles                  75102495                       # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization                1.976946                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles               3732347710                       # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles                  66567241                       # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization                1.752270                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles               3782991821                       # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles                  15923130                       # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization                0.419149                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles               3738659661                       # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles                  60255290                       # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization                1.586118                       # Percentage of cycles stage was utilized (processing insts).
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi         no_value                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle      no_value                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk        no_value                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc      no_value                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk        no_value                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle      no_value                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc      no_value                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn       no_value                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal       no_value                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.cpu.icache.replacements                 976859                       # number of replacements
system.cpu.icache.tagsinuse                509.192354                       # Cycle average of tags in use
system.cpu.icache.total_refs                 14112403                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                 977370                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                  14.439161                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle            48225021000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0            509.192354                       # Average occupied blocks per context
system.cpu.icache.occ_percent::0             0.994516                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::0            14112405                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        14112405                       # number of ReadReq hits
system.cpu.icache.demand_hits::0             14112405                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::1                    0                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         14112405                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::0            14112405                       # number of overall hits
system.cpu.icache.overall_hits::1                   0                       # number of overall hits
system.cpu.icache.overall_hits::total        14112405                       # number of overall hits
system.cpu.icache.ReadReq_misses::0           1171582                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1171582                       # number of ReadReq misses
system.cpu.icache.demand_misses::0            1171582                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::1                  0                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1171582                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::0           1171582                       # number of overall misses
system.cpu.icache.overall_misses::1                 0                       # number of overall misses
system.cpu.icache.overall_misses::total       1171582                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency    17108277000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency     17108277000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency    17108277000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::0        15283987                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     15283987                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::0         15283987                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::1                0                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     15283987                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::0        15283987                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     15283987                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::0       0.076654                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::0        0.076654                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::0       0.076654                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::0 14602.714108                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::0 14602.714108                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::0 14602.714108                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs        29000                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets       209500                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                10                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets              12                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs         2900                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 17458.333333                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.writebacks                      151                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits            194034                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits             194034                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits            194034                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses          977548                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses           977548                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses          977548                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency  11589669500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency  11589669500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency  11589669500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::0     0.063959                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::0     0.063959                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::0     0.063959                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11855.857206                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 11855.857206                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 11855.857206                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                1388966                       # number of replacements
system.cpu.dcache.tagsinuse                511.992872                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 15595787                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                1389478                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                  11.224206                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle               41598000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0            511.992872                       # Average occupied blocks per context
system.cpu.dcache.occ_percent::0             0.999986                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::0            10619576                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        10619576                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::0            4593305                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        4593305                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::0        183295                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       183295                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::0         199575                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       199575                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::0             15212881                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::1                    0                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         15212881                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::0            15212881                       # number of overall hits
system.cpu.dcache.overall_hits::1                   0                       # number of overall hits
system.cpu.dcache.overall_hits::total        15212881                       # number of overall hits
system.cpu.dcache.ReadReq_misses::0           1200515                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1200515                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::0          1568476                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1568476                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::0        17334                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        17334                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::0            2768991                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::1                  0                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        2768991                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::0           2768991                       # number of overall misses
system.cpu.dcache.overall_misses::1                 0                       # number of overall misses
system.cpu.dcache.overall_misses::total       2768991                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency    29846929000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency   52147271000                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency    254755500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency     81994200000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency    81994200000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::0        11820091                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     11820091                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::0        6161781                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      6161781                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::0       200629                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       200629                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::0       199575                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       199575                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::0         17981872                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::1                0                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     17981872                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::0        17981872                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     17981872                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::0       0.101566                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::0      0.254549                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::0     0.086398                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::0        0.153988                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::0       0.153988                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::0 24861.770990                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::0 33247.095270                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14696.867428                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::0 29611.580536                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::0 29611.580536                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs     22647500                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets   4244310000                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs              2708                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets          136112                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs  8363.183161                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 31182.482074                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks                   825388                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits            132590                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits          1264137                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits          102                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits            1396727                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits           1396727                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses         1067925                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses         304339                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses        17232                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses          1372264                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses         1372264                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency  24081352000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency   8438501500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency    195926000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency  32519853500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency  32519853500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency    906226000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency   1239305500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency   2145531500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::0     0.090348                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::0     0.049391                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0     0.085890                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::0     0.076314                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::0     0.076314                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22549.665941                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 27727.309021                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11369.893222                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 23697.957172                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 23697.957172                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                     6445                       # number of quiesce instructions executed
system.cpu.kern.inst.hwrei                     212089                       # number of hwrei instructions executed
system.cpu.kern.ipl_count::0                    75017     40.93%     40.93% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21                     240      0.13%     41.06% # number of times we switched to this ipl
system.cpu.kern.ipl_count::22                    1920      1.05%     42.10% # number of times we switched to this ipl
system.cpu.kern.ipl_count::31                  106125     57.90%    100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_count::total               183302                       # number of times we switched to this ipl
system.cpu.kern.ipl_good::0                     73650     49.28%     49.28% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21                      240      0.16%     49.44% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::22                     1920      1.28%     50.72% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31                    73650     49.28%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total                149460                       # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks::0             1857236384500     97.79%     97.79% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::21               103259500      0.01%     97.80% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22               182902000      0.01%     97.81% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31             41671857000      2.19%    100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::total         1899194403000                       # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0                  0.981777                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::31                 0.693993                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
system.cpu.kern.syscall::6                         42     12.88%     25.77% # number of syscalls executed
system.cpu.kern.syscall::12                         1      0.31%     26.07% # number of syscalls executed
system.cpu.kern.syscall::15                         1      0.31%     26.38% # number of syscalls executed
system.cpu.kern.syscall::17                        15      4.60%     30.98% # number of syscalls executed
system.cpu.kern.syscall::19                        10      3.07%     34.05% # number of syscalls executed
system.cpu.kern.syscall::20                         6      1.84%     35.89% # number of syscalls executed
system.cpu.kern.syscall::23                         4      1.23%     37.12% # number of syscalls executed
system.cpu.kern.syscall::24                         6      1.84%     38.96% # number of syscalls executed
system.cpu.kern.syscall::33                        11      3.37%     42.33% # number of syscalls executed
system.cpu.kern.syscall::41                         2      0.61%     42.94% # number of syscalls executed
system.cpu.kern.syscall::45                        54     16.56%     59.51% # number of syscalls executed
system.cpu.kern.syscall::47                         6      1.84%     61.35% # number of syscalls executed
system.cpu.kern.syscall::48                        10      3.07%     64.42% # number of syscalls executed
system.cpu.kern.syscall::54                        10      3.07%     67.48% # number of syscalls executed
system.cpu.kern.syscall::58                         1      0.31%     67.79% # number of syscalls executed
system.cpu.kern.syscall::59                         7      2.15%     69.94% # number of syscalls executed
system.cpu.kern.syscall::71                        54     16.56%     86.50% # number of syscalls executed
system.cpu.kern.syscall::73                         3      0.92%     87.42% # number of syscalls executed
system.cpu.kern.syscall::74                        16      4.91%     92.33% # number of syscalls executed
system.cpu.kern.syscall::87                         1      0.31%     92.64% # number of syscalls executed
system.cpu.kern.syscall::90                         3      0.92%     93.56% # number of syscalls executed
system.cpu.kern.syscall::92                         9      2.76%     96.32% # number of syscalls executed
system.cpu.kern.syscall::97                         2      0.61%     96.93% # number of syscalls executed
system.cpu.kern.syscall::98                         2      0.61%     97.55% # number of syscalls executed
system.cpu.kern.syscall::132                        4      1.23%     98.77% # number of syscalls executed
system.cpu.kern.syscall::144                        2      0.61%     99.39% # number of syscalls executed
system.cpu.kern.syscall::147                        2      0.61%    100.00% # number of syscalls executed
system.cpu.kern.syscall::total                    326                       # number of syscalls executed
system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::swpctx                  4176      2.16%      2.17% # number of callpals executed
system.cpu.kern.callpal::tbi                       54      0.03%      2.19% # number of callpals executed
system.cpu.kern.callpal::wrent                      7      0.00%      2.20% # number of callpals executed
system.cpu.kern.callpal::swpipl                175887     91.18%     93.38% # number of callpals executed
system.cpu.kern.callpal::rdps                    6802      3.53%     96.91% # number of callpals executed
system.cpu.kern.callpal::wrkgp                      1      0.00%     96.91% # number of callpals executed
system.cpu.kern.callpal::wrusp                      7      0.00%     96.91% # number of callpals executed
system.cpu.kern.callpal::rdusp                      9      0.00%     96.91% # number of callpals executed
system.cpu.kern.callpal::whami                      2      0.00%     96.92% # number of callpals executed
system.cpu.kern.callpal::rti                     5254      2.72%     99.64% # number of callpals executed
system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
system.cpu.kern.callpal::total                 192899                       # number of callpals executed
system.cpu.kern.mode_switch::kernel              8095                       # number of protection mode switches
system.cpu.kern.mode_switch::user                1737                       # number of protection mode switches
system.cpu.kern.mode_switch::idle                   0                       # number of protection mode switches
system.cpu.kern.mode_good::kernel                1736                      
system.cpu.kern.mode_good::user                  1737                      
system.cpu.kern.mode_good::idle                     0                      
system.cpu.kern.mode_switch_good::kernel     0.214453                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::idle       no_value                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total      no_value                       # fraction of useful protection mode switches
system.cpu.kern.mode_ticks::kernel       1895952878500     99.83%     99.83% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user           3241521500      0.17%    100.00% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle                    0      0.00%    100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context                     4177                       # number of times the context was actually changed

---------- End Simulation Statistics   ----------