path: root/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.899412                       # Number of seconds simulated
sim_ticks                                1899411597500                       # Number of ticks simulated
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 123946                       # Simulator instruction rate (inst/s)
host_tick_rate                             4137994790                       # Simulator tick rate (ticks/s)
host_mem_usage                                 343492                       # Number of bytes of host memory used
host_seconds                                   459.02                       # Real time elapsed on the host
sim_insts                                    56893410                       # Number of instructions simulated
system.l2c.replacements                        397094                       # number of replacements
system.l2c.tagsinuse                     35529.229053                       # Cycle average of tags in use
system.l2c.total_refs                         2438232                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        432488                       # Sample count of references to valid blocks.
system.l2c.avg_refs                          5.637687                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                    9244135000                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::0                 10221.529700                       # Average occupied blocks per context
system.l2c.occ_blocks::1                  2327.457536                       # Average occupied blocks per context
system.l2c.occ_blocks::2                 22980.241816                       # Average occupied blocks per context
system.l2c.occ_percent::0                    0.155968                       # Average percentage of cache occupancy
system.l2c.occ_percent::1                    0.035514                       # Average percentage of cache occupancy
system.l2c.occ_percent::2                    0.350651                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::0                    1442413                       # number of ReadReq hits
system.l2c.ReadReq_hits::1                     407625                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1850038                       # number of ReadReq hits
system.l2c.Writeback_hits::0                   800001                       # number of Writeback hits
system.l2c.Writeback_hits::total               800001                       # number of Writeback hits
system.l2c.UpgradeReq_hits::0                     188                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::1                      71                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 259                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::0                    35                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::1                    35                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                70                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::0                   148509                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::1                    19811                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               168320                       # number of ReadExReq hits
system.l2c.demand_hits::0                     1590922                       # number of demand (read+write) hits
system.l2c.demand_hits::1                      427436                       # number of demand (read+write) hits
system.l2c.demand_hits::2                           0                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2018358                       # number of demand (read+write) hits
system.l2c.overall_hits::0                    1590922                       # number of overall hits
system.l2c.overall_hits::1                     427436                       # number of overall hits
system.l2c.overall_hits::2                          0                       # number of overall hits
system.l2c.overall_hits::total                2018358                       # number of overall hits
system.l2c.ReadReq_misses::0                   301840                       # number of ReadReq misses
system.l2c.ReadReq_misses::1                     7227                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               309067                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::0                  3348                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::1                   792                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              4140                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::0                 439                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::1                 492                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total             931                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::0                 106737                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::1                  17826                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             124563                       # number of ReadExReq misses
system.l2c.demand_misses::0                    408577                       # number of demand (read+write) misses
system.l2c.demand_misses::1                     25053                       # number of demand (read+write) misses
system.l2c.demand_misses::2                         0                       # number of demand (read+write) misses
system.l2c.demand_misses::total                433630                       # number of demand (read+write) misses
system.l2c.overall_misses::0                   408577                       # number of overall misses
system.l2c.overall_misses::1                    25053                       # number of overall misses
system.l2c.overall_misses::2                        0                       # number of overall misses
system.l2c.overall_misses::total               433630                       # number of overall misses
system.l2c.ReadReq_miss_latency           16078822000                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency            5852000                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency          5401500                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency          6533699500                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency            22612521500                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency           22612521500                       # number of overall miss cycles
system.l2c.ReadReq_accesses::0                1744253                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::1                 414852                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2159105                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::0               800001                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           800001                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::0                3536                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::1                 863                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            4399                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::0               474                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::1               527                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          1001                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::0               255246                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::1                37637                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           292883                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::0                 1999499                       # number of demand (read+write) accesses
system.l2c.demand_accesses::1                  452489                       # number of demand (read+write) accesses
system.l2c.demand_accesses::2                       0                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2451988                       # number of demand (read+write) accesses
system.l2c.overall_accesses::0                1999499                       # number of overall (read+write) accesses
system.l2c.overall_accesses::1                 452489                       # number of overall (read+write) accesses
system.l2c.overall_accesses::2                      0                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2451988                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::0              0.173048                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::1              0.017421                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::0           0.946833                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::1           0.917729                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::0         0.926160                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::1         0.933586                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::0            0.418173                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::1            0.473630                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::0               0.204340                       # miss rate for demand accesses
system.l2c.demand_miss_rate::1               0.055367                       # miss rate for demand accesses
system.l2c.demand_miss_rate::2               no_value                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           no_value                       # miss rate for demand accesses
system.l2c.overall_miss_rate::0              0.204340                       # miss rate for overall accesses
system.l2c.overall_miss_rate::1              0.055367                       # miss rate for overall accesses
system.l2c.overall_miss_rate::2              no_value                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          no_value                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::0   53269.354625                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::1   2224826.622388                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::2            inf                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::0  1747.909200                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::1  7388.888889                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::2          inf                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::0 12304.100228                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::1 10978.658537                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::2          inf                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total          inf                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::0 61213.070444                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::1 366526.394031                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::2          inf                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::0    55344.577644                       # average overall miss latency
system.l2c.demand_avg_miss_latency::1    902587.374765                       # average overall miss latency
system.l2c.demand_avg_miss_latency::2             inf                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.l2c.overall_avg_miss_latency::0   55344.577644                       # average overall miss latency
system.l2c.overall_avg_miss_latency::1   902587.374765                       # average overall miss latency
system.l2c.overall_avg_miss_latency::2            inf                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks                          122463                       # number of writebacks
system.l2c.ReadReq_mshr_hits                       17                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits                        17                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits                       17                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses                 309050                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses                4140                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses               931                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses               124563                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses                  433613                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses                 433613                       # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency      12366985500                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency     165615000                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency     37241500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency     5018687000                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency       17385672500                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency      17385672500                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency    838004500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency   1515144998                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency   2353149498                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::0         0.177182                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::1         0.744964                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::2              inf                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::0      1.170814                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::1      4.797219                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::2           inf                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::0     1.964135                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::1     1.766603                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::2          inf                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::0       0.488012                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::1       3.309589                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::2            inf                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::0          0.216861                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::1          0.958284                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::2               inf                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total           inf                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::0         0.216861                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::1         0.958284                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::2              inf                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency 40016.131694                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency 40003.623188                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40001.611171                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency 40290.351067                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency  40094.906057                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency 40094.906057                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.iocache.replacements                     41701                       # number of replacements
system.iocache.tagsinuse                     0.379564                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                     41717                       # Sample count of references to valid blocks.
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.warmup_cycle              1708346603000                       # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::1                 0.379564                       # Average occupied blocks per context
system.iocache.occ_percent::1                0.023723                       # Average percentage of cache occupancy
system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
system.iocache.overall_hits::0                      0                       # number of overall hits
system.iocache.overall_hits::1                      0                       # number of overall hits
system.iocache.overall_hits::total                  0                       # number of overall hits
system.iocache.ReadReq_misses::1                  179                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              179                       # number of ReadReq misses
system.iocache.WriteReq_misses::1               41552                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
system.iocache.demand_misses::1                 41731                       # number of demand (read+write) misses
system.iocache.demand_misses::total             41731                       # number of demand (read+write) misses
system.iocache.overall_misses::0                    0                       # number of overall misses
system.iocache.overall_misses::1                41731                       # number of overall misses
system.iocache.overall_misses::total            41731                       # number of overall misses
system.iocache.ReadReq_miss_latency          20618998                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency       5720800806                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency         5741419804                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency        5741419804                       # number of overall miss cycles
system.iocache.ReadReq_accesses::1                179                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            179                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::1             41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
system.iocache.demand_accesses::1               41731                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           41731                       # number of demand (read+write) accesses
system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
system.iocache.overall_accesses::1              41731                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          41731                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::1                 1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::1                1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
system.iocache.demand_miss_rate::1                  1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
system.iocache.overall_miss_rate::1                 1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::1 115189.932961                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::0          inf                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::1 137678.109501                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::0          inf                       # average overall miss latency
system.iocache.demand_avg_miss_latency::1 137581.649230                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.iocache.overall_avg_miss_latency::0          inf                       # average overall miss latency
system.iocache.overall_avg_miss_latency::1 137581.649230                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs      64641068                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                10457                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs  6181.607344                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks                       41522                       # number of writebacks
system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
system.iocache.ReadReq_mshr_misses                179                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses             41552                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses               41731                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses              41731                       # number of overall MSHR misses
system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.iocache.ReadReq_mshr_miss_latency     11310998                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency   3559941996                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency    3571252994                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency   3571252994                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::1            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::0          inf                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::1            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::0           inf                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::1             1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::1            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency 63189.932961                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency 85674.383808                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency 85577.939517                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency 85577.939517                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.cpu0.dtb.fetch_hits                          0                       # ITB hits
system.cpu0.dtb.fetch_misses                        0                       # ITB misses
system.cpu0.dtb.fetch_acv                           0                       # ITB acv
system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu0.dtb.read_hits                     8691348                       # DTB read hits
system.cpu0.dtb.read_misses                     30841                       # DTB read misses
system.cpu0.dtb.read_acv                          585                       # DTB read access violations
system.cpu0.dtb.read_accesses                  626526                       # DTB read accesses
system.cpu0.dtb.write_hits                    5727483                       # DTB write hits
system.cpu0.dtb.write_misses                     5665                       # DTB write misses
system.cpu0.dtb.write_acv                         282                       # DTB write access violations
system.cpu0.dtb.write_accesses                 212486                       # DTB write accesses
system.cpu0.dtb.data_hits                    14418831                       # DTB hits
system.cpu0.dtb.data_misses                     36506                       # DTB misses
system.cpu0.dtb.data_acv                          867                       # DTB access violations
system.cpu0.dtb.data_accesses                  839012                       # DTB accesses
system.cpu0.itb.fetch_hits                    1018007                       # ITB hits
system.cpu0.itb.fetch_misses                    28254                       # ITB misses
system.cpu0.itb.fetch_acv                         951                       # ITB acv
system.cpu0.itb.fetch_accesses                1046261                       # ITB accesses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.read_acv                            0                       # DTB read access violations
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.write_acv                           0                       # DTB write access violations
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.data_hits                           0                       # DTB hits
system.cpu0.itb.data_misses                         0                       # DTB misses
system.cpu0.itb.data_acv                            0                       # DTB access violations
system.cpu0.itb.data_accesses                       0                       # DTB accesses
system.cpu0.numCycles                       103036446                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.BPredUnit.lookups                12345310                       # Number of BP lookups
system.cpu0.BPredUnit.condPredicted          10395868                       # Number of conditional branches predicted
system.cpu0.BPredUnit.condIncorrect            412413                       # Number of conditional branches incorrect
system.cpu0.BPredUnit.BTBLookups             11143165                       # Number of BTB lookups
system.cpu0.BPredUnit.BTBHits                 5756291                       # Number of BTB hits
system.cpu0.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.BPredUnit.usedRAS                  808447                       # Number of times the RAS was used to get a target.
system.cpu0.BPredUnit.RASInCorrect              32944                       # Number of incorrect RAS predictions.
system.cpu0.fetch.icacheStallCycles          25643568                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                      63130050                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                   12345310                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches           6564738                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                     12229123                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                1931790                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.BlockedCycles              31463202                       # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles               31044                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles       192852                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       226876                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles           96                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                  7797411                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               265802                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.rateDist::samples          71034720                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             0.888721                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.206546                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                58805597     82.78%     82.78% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                  896633      1.26%     84.05% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                 1683822      2.37%     86.42% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                  790380      1.11%     87.53% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                 2590451      3.65%     91.18% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                  578678      0.81%     91.99% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                  651939      0.92%     92.91% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                  969955      1.37%     94.27% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 4067265      5.73%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total            71034720                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.119815                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.612696                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                26620678                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             31169441                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                 11195503                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles               833782                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               1215315                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved              497181                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred                32875                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              61799188                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts                97991                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               1215315                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                27633845                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles               10392034                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      17602675                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                 10482679                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles              3708170                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              58338786                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                 6838                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents                387997                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents              1347242                       # Number of times rename has blocked due to LSQ full
system.cpu0.rename.RenamedOperands           39031988                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups             70900966                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups        70475489                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups           425477                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             33170605                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                 5861375                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts           1485068                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts        227968                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                 10243220                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads             9180149                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores            6097470                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1603652                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         1903642                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  51204618                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded            1864754                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 49739725                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued            70469                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined        6805118                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined      3728302                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved       1267762                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples     71034720                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.700217                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.322322                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           48628565     68.46%     68.46% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1           10107628     14.23%     82.69% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            4889823      6.88%     89.57% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            3044033      4.29%     93.86% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            2225901      3.13%     96.99% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5            1246231      1.75%     98.74% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6             700109      0.99%     99.73% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             154501      0.22%     99.95% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8              37929      0.05%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total       71034720                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                  52156     10.93%     10.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     0      0.00%     10.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%     10.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     10.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     10.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     10.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     10.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     10.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     10.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     10.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     10.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     10.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     10.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     10.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     10.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     10.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     10.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     10.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     10.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     10.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     10.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     10.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     10.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     10.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     10.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     10.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     10.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     10.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     10.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                267781     56.13%     67.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               157153     32.94%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass             3328      0.01%      0.01% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             33971995     68.30%     68.31% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               53580      0.11%     68.41% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     68.41% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd              15560      0.03%     68.45% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.45% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.45% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.45% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv               1654      0.00%     68.45% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.45% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.45% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.45% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.45% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.45% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.45% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.45% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.45% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.45% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.45% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.45% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.45% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.45% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.45% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.45% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.45% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.45% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     68.45% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.45% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.45% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.45% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead             9077168     18.25%     86.70% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite            5791424     11.64%     98.34% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess            825016      1.66%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              49739725                       # Type of FU issued
system.cpu0.iq.rate                          0.482739                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                     477090                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.009592                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         170451707                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         59601257                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     48417922                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads             610021                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes            293075                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses       290010                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              49893944                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                 319543                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          495668                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      1332465                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses        15476                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        20341                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores       527918                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads        14091                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked       218656                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               1215315                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                6999311                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles               544202                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           56199276                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts           754553                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts              9180149                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts             6097470                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts           1645846                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                470730                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                 6896                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         20341                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        291584                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       326384                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              617968                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             49204821                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts              8748371                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           534903                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                      3129904                       # number of nop insts executed
system.cpu0.iew.exec_refs                    14495988                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                 7765506                       # Number of branches executed
system.cpu0.iew.exec_stores                   5747617                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.477548                       # Inst execution rate
system.cpu0.iew.wb_sent                      48811342                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     48707932                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 23956930                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 32092147                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.472725                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.746504                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitCommittedInsts      48759720                       # The number of committed instructions
system.cpu0.commit.commitSquashedInsts        7342909                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls         596992                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           565842                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples     69819405                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.698369                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.595257                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     51124042     73.22%     73.22% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1      8032267     11.50%     84.73% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      4140271      5.93%     90.66% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      2329968      3.34%     93.99% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4      1273302      1.82%     95.82% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       518646      0.74%     96.56% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6       361032      0.52%     97.08% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       714639      1.02%     98.10% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1325238      1.90%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total     69819405                       # Number of insts commited each cycle
system.cpu0.commit.count                     48759720                       # Number of instructions committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      13417236                       # Number of memory references committed
system.cpu0.commit.loads                      7847684                       # Number of loads committed
system.cpu0.commit.membars                     202015                       # Number of memory barriers committed
system.cpu0.commit.branches                   7296729                       # Number of branches committed
system.cpu0.commit.fp_insts                    287598                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 45136958                       # Number of committed integer instructions.
system.cpu0.commit.function_calls              626830                       # Number of function calls committed.
system.cpu0.commit.bw_lim_events              1325238                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                   124403287                       # The number of ROB reads
system.cpu0.rob.rob_writes                  113421475                       # The number of ROB writes
system.cpu0.timesIdled                        1076474                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                       32001726                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.committedInsts                   45967748                       # Number of Instructions Simulated
system.cpu0.committedInsts_total             45967748                       # Number of Instructions Simulated
system.cpu0.cpi                              2.241494                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        2.241494                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.446131                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.446131                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads                64511715                       # number of integer regfile reads
system.cpu0.int_regfile_writes               35217125                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                   141815                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                  144143                       # number of floating regfile writes
system.cpu0.misc_regfile_reads                1768684                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                843519                       # number of misc regfile writes
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi         no_value                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle      no_value                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk        no_value                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc      no_value                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk        no_value                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle      no_value                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc      no_value                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn       no_value                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal       no_value                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.cpu0.icache.replacements                880531                       # number of replacements
system.cpu0.icache.tagsinuse               509.999835                       # Cycle average of tags in use
system.cpu0.icache.total_refs                 6871052                       # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs                881041                       # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs                  7.798788                       # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle           23352841000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::0           509.999835                       # Average occupied blocks per context
system.cpu0.icache.occ_percent::0            0.996093                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::0            6871052                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total        6871052                       # number of ReadReq hits
system.cpu0.icache.demand_hits::0             6871052                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::1                   0                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total         6871052                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::0            6871052                       # number of overall hits
system.cpu0.icache.overall_hits::1                  0                       # number of overall hits
system.cpu0.icache.overall_hits::total        6871052                       # number of overall hits
system.cpu0.icache.ReadReq_misses::0           926359                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       926359                       # number of ReadReq misses
system.cpu0.icache.demand_misses::0            926359                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::1                 0                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        926359                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::0           926359                       # number of overall misses
system.cpu0.icache.overall_misses::1                0                       # number of overall misses
system.cpu0.icache.overall_misses::total       926359                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency   13849490998                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency    13849490998                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency   13849490998                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::0        7797411                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total      7797411                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::0         7797411                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total      7797411                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::0        7797411                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total      7797411                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::0      0.118803                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::0       0.118803                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::0      0.118803                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::0 14950.457650                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::0 14950.457650                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::0 14950.457650                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs      1091498                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              105                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 10395.219048                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.writebacks                     208                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits            45158                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits             45158                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits            45158                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses         881201                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses          881201                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses         881201                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency  10516036498                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency  10516036498                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency  10516036498                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::0     0.113012                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::0     0.113012                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::0     0.113012                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11933.754612                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency 11933.754612                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency 11933.754612                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.replacements               1121199                       # number of replacements
system.cpu0.dcache.tagsinuse               488.854716                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                10572300                       # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs               1121711                       # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs                  9.425155                       # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::0           489.854716                       # Average occupied blocks per context
system.cpu0.dcache.occ_blocks::1            -1.000000                       # Average occupied blocks per context
system.cpu0.dcache.occ_percent::0            0.956747                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::1           -0.001953                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::0            6494021                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        6494021                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::0           3693282                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       3693282                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::0       174657                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       174657                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::0        196468                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       196468                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::0            10187303                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        10187303                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::0           10187303                       # number of overall hits
system.cpu0.dcache.overall_hits::1                  0                       # number of overall hits
system.cpu0.dcache.overall_hits::total       10187303                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::0          1375687                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      1375687                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::0         1662707                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1662707                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::0        20152                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        20152                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::0         3348                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total         3348                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::0           3038394                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       3038394                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::0          3038394                       # number of overall misses
system.cpu0.dcache.overall_misses::1                0                       # number of overall misses
system.cpu0.dcache.overall_misses::total      3038394                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency   31827617500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency  51165322075                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency    294994000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency     41962000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency    82992939575                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency   82992939575                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::0        7869708                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      7869708                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::0       5355989                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      5355989                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::0       194809                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       194809                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::0       199816                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       199816                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::0        13225697                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     13225697                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::0       13225697                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     13225697                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::0      0.174808                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::0     0.310439                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::0     0.103445                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::0     0.016755                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::0       0.229734                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::0      0.229734                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::0 23135.798695                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::0 30772.302080                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 14638.447797                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 12533.452808                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::0 27314.739160                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::0 27314.739160                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs    855518470                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets       221500                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs            97807                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets             10                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs  8747.006554                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets        22150                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks                  602926                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits           516336                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits         1401114                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits         4413                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits           1917450                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits          1917450                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses         859351                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses        261593                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses        15739                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses         3348                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses         1120944                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses        1120944                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency  21884756500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency   7717990970                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency    167906500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency     31911000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency  29602747470                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency  29602747470                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency    634931500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency   1090823998                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency   1725755498                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::0     0.109197                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::0     0.048841                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0     0.080792                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0     0.016755                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::0     0.084755                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::0     0.084755                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 25466.609686                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 29503.813061                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 10668.180952                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency  9531.362007                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency 26408.765710                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency 26408.765710                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits                          0                       # ITB hits
system.cpu1.dtb.fetch_misses                        0                       # ITB misses
system.cpu1.dtb.fetch_acv                           0                       # ITB acv
system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu1.dtb.read_hits                     2335038                       # DTB read hits
system.cpu1.dtb.read_misses                     11141                       # DTB read misses
system.cpu1.dtb.read_acv                           15                       # DTB read access violations
system.cpu1.dtb.read_accesses                  329726                       # DTB read accesses
system.cpu1.dtb.write_hits                    1301059                       # DTB write hits
system.cpu1.dtb.write_misses                     3075                       # DTB write misses
system.cpu1.dtb.write_acv                          63                       # DTB write access violations
system.cpu1.dtb.write_accesses                 125932                       # DTB write accesses
system.cpu1.dtb.data_hits                     3636097                       # DTB hits
system.cpu1.dtb.data_misses                     14216                       # DTB misses
system.cpu1.dtb.data_acv                           78                       # DTB access violations
system.cpu1.dtb.data_accesses                  455658                       # DTB accesses
system.cpu1.itb.fetch_hits                     423788                       # ITB hits
system.cpu1.itb.fetch_misses                     7837                       # ITB misses
system.cpu1.itb.fetch_acv                         166                       # ITB acv
system.cpu1.itb.fetch_accesses                 431625                       # ITB accesses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.read_acv                            0                       # DTB read access violations
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.write_acv                           0                       # DTB write access violations
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.data_hits                           0                       # DTB hits
system.cpu1.itb.data_misses                         0                       # DTB misses
system.cpu1.itb.data_acv                            0                       # DTB access violations
system.cpu1.itb.data_accesses                       0                       # DTB accesses
system.cpu1.numCycles                        20152954                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.BPredUnit.lookups                 3242658                       # Number of BP lookups
system.cpu1.BPredUnit.condPredicted           2662310                       # Number of conditional branches predicted
system.cpu1.BPredUnit.condIncorrect            131441                       # Number of conditional branches incorrect
system.cpu1.BPredUnit.BTBLookups              2892914                       # Number of BTB lookups
system.cpu1.BPredUnit.BTBHits                 1375784                       # Number of BTB hits
system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.BPredUnit.usedRAS                  235158                       # Number of times the RAS was used to get a target.
system.cpu1.BPredUnit.RASInCorrect               7774                       # Number of incorrect RAS predictions.
system.cpu1.fetch.icacheStallCycles           6188689                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                      16200802                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                    3242658                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches           1610942                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                      3090469                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                 613653                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.BlockedCycles               7714239                       # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles               27241                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles        65046                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles       159598                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles           12                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                  1940544                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes                74817                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples          17655267                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             0.917619                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.257026                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                14564798     82.50%     82.50% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                  197815      1.12%     83.62% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                  462974      2.62%     86.24% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                  255072      1.44%     87.68% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                  513820      2.91%     90.59% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                  162072      0.92%     91.51% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                  211046      1.20%     92.71% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                  121453      0.69%     93.39% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                 1166217      6.61%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total            17655267                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.160902                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.803892                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                 6415483                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles              7821687                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                  2861971                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles               154408                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles                401717                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved              149324                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred                 8351                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              15726471                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts                21041                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles                401717                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                 6681295                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                2118018                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles       4943945                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                  2656010                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles               854280                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              14736815                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                  186                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                221815                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents               138242                       # Number of times rename has blocked due to LSQ full
system.cpu1.rename.RenamedOperands            9911157                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups             18088761                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups        17988130                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups           100631                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps              7897558                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                 2013599                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts            424269                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts         36275                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                  2592161                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads             2485755                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores            1426985                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads           360752                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores          285996                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                  12852454                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded             484885                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                 12271073                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued            26221                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined        2300844                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined      1315458                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        356394                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples     17655267                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.695038                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.354056                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0           12407145     70.27%     70.27% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1            2235941     12.66%     82.94% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2            1035355      5.86%     88.80% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3             796484      4.51%     93.31% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4             626149      3.55%     96.86% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5             333560      1.89%     98.75% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6             156466      0.89%     99.64% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7              49558      0.28%     99.92% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8              14609      0.08%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total       17655267                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                  13105      7.34%      7.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     0      0.00%      7.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      7.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      7.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      7.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      7.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      7.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      7.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      7.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      7.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      7.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      7.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      7.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      7.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      7.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      7.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      7.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      7.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      7.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      7.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      7.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      7.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      7.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      7.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      7.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      7.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      7.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      7.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      7.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                 95150     53.29%     60.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite                70292     39.37%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass             3979      0.03%      0.03% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu              8216703     66.96%     66.99% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               19600      0.16%     67.15% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     67.15% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd              11030      0.09%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv               1988      0.02%     67.26% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     67.26% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     67.26% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     67.26% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     67.26% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     67.26% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     67.26% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     67.26% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     67.26% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     67.26% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     67.26% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     67.26% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     67.26% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     67.26% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.26% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     67.26% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     67.26% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     67.26% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     67.26% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     67.26% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.26% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     67.26% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead             2431476     19.81%     87.07% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite            1328460     10.83%     97.90% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess            257837      2.10%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total              12271073                       # Type of FU issued
system.cpu1.iq.rate                          0.608897                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                     178547                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.014550                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads          42255695                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         15570864                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses     11866318                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads             146486                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes             71642                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses        70264                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses              12369614                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                  76027                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads          105474                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads       463598                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses         9284                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation         4789                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores       195743                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads         5212                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked        50812                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles                401717                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                1622444                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles                62821                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           14027082                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts           177744                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts              2485755                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts             1426985                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            441055                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                 11459                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                 3097                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents          4789                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect        106850                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect        88794                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              195644                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts             12103351                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts              2352431                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts           167722                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       689743                       # number of nop insts executed
system.cpu1.iew.exec_refs                     3661778                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                 1907962                       # Number of branches executed
system.cpu1.iew.exec_stores                   1309347                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.600575                       # Inst execution rate
system.cpu1.iew.wb_sent                      11974198                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                     11936582                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                  5946561                       # num instructions producing a value
system.cpu1.iew.wb_consumers                  8293064                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.592299                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.717052                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitCommittedInsts      11515527                       # The number of committed instructions
system.cpu1.commit.commitSquashedInsts        2436187                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls         128491                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           177413                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples     17253550                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.667429                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.563448                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     12827961     74.35%     74.35% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1      1952306     11.32%     85.67% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2       928648      5.38%     91.05% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3       493505      2.86%     93.91% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4       338427      1.96%     95.87% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5       153865      0.89%     96.76% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6       124614      0.72%     97.48% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7       119099      0.69%     98.17% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8       315125      1.83%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total     17253550                       # Number of insts commited each cycle
system.cpu1.commit.count                     11515527                       # Number of instructions committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                       3253399                       # Number of memory references committed
system.cpu1.commit.loads                      2022157                       # Number of loads committed
system.cpu1.commit.membars                      41280                       # Number of memory barriers committed
system.cpu1.commit.branches                   1729331                       # Number of branches committed
system.cpu1.commit.fp_insts                     68665                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                 10682634                       # Number of committed integer instructions.
system.cpu1.commit.function_calls              174972                       # Number of function calls committed.
system.cpu1.commit.bw_lim_events               315125                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                    30796624                       # The number of ROB reads
system.cpu1.rob.rob_writes                   28304513                       # The number of ROB writes
system.cpu1.timesIdled                         230784                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                        2497687                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.committedInsts                   10925662                       # Number of Instructions Simulated
system.cpu1.committedInsts_total             10925662                       # Number of Instructions Simulated
system.cpu1.cpi                              1.844552                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.844552                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.542137                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.542137                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                15857410                       # number of integer regfile reads
system.cpu1.int_regfile_writes                8648406                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                    40377                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                   39511                       # number of floating regfile writes
system.cpu1.misc_regfile_reads                 441161                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                195544                       # number of misc regfile writes
system.cpu1.icache.replacements                205961                       # number of replacements
system.cpu1.icache.tagsinuse               502.866762                       # Cycle average of tags in use
system.cpu1.icache.total_refs                 1723284                       # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs                206473                       # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs                  8.346292                       # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle          1708291874000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::0           502.866762                       # Average occupied blocks per context
system.cpu1.icache.occ_percent::0            0.982162                       # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::0            1723284                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total        1723284                       # number of ReadReq hits
system.cpu1.icache.demand_hits::0             1723284                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::1                   0                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total         1723284                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::0            1723284                       # number of overall hits
system.cpu1.icache.overall_hits::1                  0                       # number of overall hits
system.cpu1.icache.overall_hits::total        1723284                       # number of overall hits
system.cpu1.icache.ReadReq_misses::0           217260                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       217260                       # number of ReadReq misses
system.cpu1.icache.demand_misses::0            217260                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::1                 0                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        217260                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::0           217260                       # number of overall misses
system.cpu1.icache.overall_misses::1                0                       # number of overall misses
system.cpu1.icache.overall_misses::total       217260                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency    3300371999                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency     3300371999                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency    3300371999                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::0        1940544                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total      1940544                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::0         1940544                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total      1940544                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::0        1940544                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total      1940544                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::0      0.111958                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::0       0.111958                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::0      0.111958                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::0 15190.886491                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::0 15190.886491                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::0 15190.886491                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs       349000                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs               33                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs 10575.757576                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.writebacks                      52                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_hits            10723                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits             10723                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits            10723                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses         206537                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses          206537                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses         206537                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency   2520725000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency   2520725000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency   2520725000                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::0     0.106433                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::0     0.106433                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::0     0.106433                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency 12204.713925                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency 12204.713925                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency 12204.713925                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.replacements                248685                       # number of replacements
system.cpu1.dcache.tagsinuse               476.656972                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                 2836087                       # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs                248990                       # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs                 11.390365                       # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle           39851697000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::0           476.656972                       # Average occupied blocks per context
system.cpu1.dcache.occ_percent::0            0.930971                       # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::0            1838875                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        1838875                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::0            950135                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total        950135                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::0        25812                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        25812                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::0         24969                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        24969                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::0             2789010                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         2789010                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::0            2789010                       # number of overall hits
system.cpu1.dcache.overall_hits::1                  0                       # number of overall hits
system.cpu1.dcache.overall_hits::total        2789010                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::0           315850                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       315850                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::0          245510                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       245510                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::0         5339                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total         5339                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::0         3179                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total         3179                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::0            561360                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        561360                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::0           561360                       # number of overall misses
system.cpu1.dcache.overall_misses::1                0                       # number of overall misses
system.cpu1.dcache.overall_misses::total       561360                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency    4714821500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency   8024030885                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency     65075500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency     42948000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency    12738852385                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency   12738852385                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::0        2154725                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      2154725                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::0       1195645                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      1195645                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::0        31151                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        31151                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::0        28148                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        28148                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::0         3350370                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      3350370                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::0        3350370                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      3350370                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::0      0.146585                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::0     0.205337                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::0     0.171391                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::0     0.112939                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::0       0.167552                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::0      0.167552                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::0 14927.406997                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::0 32683.112236                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 12188.705750                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 13509.908776                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::0 22692.839506                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::0 22692.839506                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs    135872392                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets       106000                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs            10757                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              4                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12631.067398                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets        26500                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks                  196815                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits            98942                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits          203211                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits         1094                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits            302153                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits           302153                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses         216908                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses         42299                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses         4245                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses         3179                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses          259207                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses         259207                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency   2649753500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency   1268849871                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency     33277000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency     33400500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency   3918603371                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency   3918603371                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency    300850000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency    586892500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency    887742500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::0     0.100666                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::0     0.035378                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0     0.136272                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0     0.112939                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::0     0.077367                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::0     0.077367                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12216.024766                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 29997.160004                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency  7839.104829                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 10506.605851                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency 15117.660291                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency 15117.660291                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    5037                       # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei                    186073                       # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0                   65315     40.13%     40.13% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21                    237      0.15%     40.27% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22                   1923      1.18%     41.46% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30                    222      0.14%     41.59% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31                  95069     58.41%    100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total              162766                       # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0                    63957     49.17%     49.17% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21                     237      0.18%     49.35% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22                    1923      1.48%     50.83% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30                     222      0.17%     51.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31                   63735     49.00%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total               130074                       # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0            1863353937000     98.10%     98.10% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21               90928000      0.00%     98.11% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22              390512500      0.02%     98.13% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30               85006500      0.00%     98.13% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31            35490372000      1.87%    100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total        1899410756000                       # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0                 0.979208                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31                0.670408                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2                         8      3.72%      3.72% # number of syscalls executed
system.cpu0.kern.syscall::3                        18      8.37%     12.09% # number of syscalls executed
system.cpu0.kern.syscall::4                         3      1.40%     13.49% # number of syscalls executed
system.cpu0.kern.syscall::6                        32     14.88%     28.37% # number of syscalls executed
system.cpu0.kern.syscall::12                        1      0.47%     28.84% # number of syscalls executed
system.cpu0.kern.syscall::17                        8      3.72%     32.56% # number of syscalls executed
system.cpu0.kern.syscall::19                       10      4.65%     37.21% # number of syscalls executed
system.cpu0.kern.syscall::20                        6      2.79%     40.00% # number of syscalls executed
system.cpu0.kern.syscall::23                        1      0.47%     40.47% # number of syscalls executed
system.cpu0.kern.syscall::24                        3      1.40%     41.86% # number of syscalls executed
system.cpu0.kern.syscall::33                        6      2.79%     44.65% # number of syscalls executed
system.cpu0.kern.syscall::41                        2      0.93%     45.58% # number of syscalls executed
system.cpu0.kern.syscall::45                       33     15.35%     60.93% # number of syscalls executed
system.cpu0.kern.syscall::47                        3      1.40%     62.33% # number of syscalls executed
system.cpu0.kern.syscall::48                       10      4.65%     66.98% # number of syscalls executed
system.cpu0.kern.syscall::54                       10      4.65%     71.63% # number of syscalls executed
system.cpu0.kern.syscall::58                        1      0.47%     72.09% # number of syscalls executed
system.cpu0.kern.syscall::59                        6      2.79%     74.88% # number of syscalls executed
system.cpu0.kern.syscall::71                       23     10.70%     85.58% # number of syscalls executed
system.cpu0.kern.syscall::73                        3      1.40%     86.98% # number of syscalls executed
system.cpu0.kern.syscall::74                        6      2.79%     89.77% # number of syscalls executed
system.cpu0.kern.syscall::87                        1      0.47%     90.23% # number of syscalls executed
system.cpu0.kern.syscall::90                        3      1.40%     91.63% # number of syscalls executed
system.cpu0.kern.syscall::92                        9      4.19%     95.81% # number of syscalls executed
system.cpu0.kern.syscall::97                        2      0.93%     96.74% # number of syscalls executed
system.cpu0.kern.syscall::98                        2      0.93%     97.67% # number of syscalls executed
system.cpu0.kern.syscall::132                       1      0.47%     98.14% # number of syscalls executed
system.cpu0.kern.syscall::144                       2      0.93%     99.07% # number of syscalls executed
system.cpu0.kern.syscall::147                       2      0.93%    100.00% # number of syscalls executed
system.cpu0.kern.syscall::total                   215                       # number of syscalls executed
system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::wripir                  307      0.18%      0.18% # number of callpals executed
system.cpu0.kern.callpal::wrmces                    1      0.00%      0.18% # number of callpals executed
system.cpu0.kern.callpal::wrfen                     1      0.00%      0.18% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.18% # number of callpals executed
system.cpu0.kern.callpal::swpctx                 3778      2.20%      2.39% # number of callpals executed
system.cpu0.kern.callpal::tbi                      50      0.03%      2.42% # number of callpals executed
system.cpu0.kern.callpal::wrent                     7      0.00%      2.42% # number of callpals executed
system.cpu0.kern.callpal::swpipl               155399     90.68%     93.10% # number of callpals executed
system.cpu0.kern.callpal::rdps                   6322      3.69%     96.79% # number of callpals executed
system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.79% # number of callpals executed
system.cpu0.kern.callpal::wrusp                     2      0.00%     96.79% # number of callpals executed
system.cpu0.kern.callpal::rdusp                     9      0.01%     96.80% # number of callpals executed
system.cpu0.kern.callpal::whami                     2      0.00%     96.80% # number of callpals executed
system.cpu0.kern.callpal::rti                    4984      2.91%     99.71% # number of callpals executed
system.cpu0.kern.callpal::callsys                 369      0.22%     99.92% # number of callpals executed
system.cpu0.kern.callpal::imb                     135      0.08%    100.00% # number of callpals executed
system.cpu0.kern.callpal::total                171369                       # number of callpals executed
system.cpu0.kern.mode_switch::kernel             7417                       # number of protection mode switches
system.cpu0.kern.mode_switch::user               1246                       # number of protection mode switches
system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
system.cpu0.kern.mode_good::kernel               1245                      
system.cpu0.kern.mode_good::user                 1246                      
system.cpu0.kern.mode_good::idle                    0                      
system.cpu0.kern.mode_switch_good::kernel     0.167858                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle      no_value                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total     no_value                       # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel      1897486158000     99.90%     99.90% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user          1924590000      0.10%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context                    3779                       # number of times the context was actually changed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    4032                       # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei                     54228                       # number of hwrei instructions executed
system.cpu1.kern.ipl_count::0                   17280     37.82%     37.82% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22                   1921      4.20%     42.02% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30                    307      0.67%     42.69% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31                  26187     57.31%    100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total               45695                       # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0                    17261     47.36%     47.36% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22                    1921      5.27%     52.64% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30                     307      0.84%     53.48% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31                   16954     46.52%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total                36443                       # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0            1869444423500     98.44%     98.44% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22              345691000      0.02%     98.46% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30              121909500      0.01%     98.46% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31            29169069500      1.54%    100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total        1899081093500                       # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0                 0.998900                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::31                0.647420                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::3                        12     10.81%     10.81% # number of syscalls executed
system.cpu1.kern.syscall::4                         1      0.90%     11.71% # number of syscalls executed
system.cpu1.kern.syscall::6                        10      9.01%     20.72% # number of syscalls executed
system.cpu1.kern.syscall::15                        1      0.90%     21.62% # number of syscalls executed
system.cpu1.kern.syscall::17                        7      6.31%     27.93% # number of syscalls executed
system.cpu1.kern.syscall::23                        3      2.70%     30.63% # number of syscalls executed
system.cpu1.kern.syscall::24                        3      2.70%     33.33% # number of syscalls executed
system.cpu1.kern.syscall::33                        5      4.50%     37.84% # number of syscalls executed
system.cpu1.kern.syscall::45                       21     18.92%     56.76% # number of syscalls executed
system.cpu1.kern.syscall::47                        3      2.70%     59.46% # number of syscalls executed
system.cpu1.kern.syscall::59                        1      0.90%     60.36% # number of syscalls executed
system.cpu1.kern.syscall::71                       31     27.93%     88.29% # number of syscalls executed
system.cpu1.kern.syscall::74                       10      9.01%     97.30% # number of syscalls executed
system.cpu1.kern.syscall::132                       3      2.70%    100.00% # number of syscalls executed
system.cpu1.kern.syscall::total                   111                       # number of syscalls executed
system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu1.kern.callpal::wripir                  222      0.47%      0.47% # number of callpals executed
system.cpu1.kern.callpal::wrmces                    1      0.00%      0.47% # number of callpals executed
system.cpu1.kern.callpal::wrfen                     1      0.00%      0.48% # number of callpals executed
system.cpu1.kern.callpal::swpctx                  871      1.85%      2.32% # number of callpals executed
system.cpu1.kern.callpal::tbi                       3      0.01%      2.33% # number of callpals executed
system.cpu1.kern.callpal::wrent                     7      0.01%      2.34% # number of callpals executed
system.cpu1.kern.callpal::swpipl                40736     86.30%     88.64% # number of callpals executed
system.cpu1.kern.callpal::rdps                   2431      5.15%     93.79% # number of callpals executed
system.cpu1.kern.callpal::wrkgp                     1      0.00%     93.79% # number of callpals executed
system.cpu1.kern.callpal::wrusp                     5      0.01%     93.80% # number of callpals executed
system.cpu1.kern.callpal::whami                     3      0.01%     93.81% # number of callpals executed
system.cpu1.kern.callpal::rti                    2730      5.78%     99.59% # number of callpals executed
system.cpu1.kern.callpal::callsys                 146      0.31%     99.90% # number of callpals executed
system.cpu1.kern.callpal::imb                      45      0.10%    100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
system.cpu1.kern.callpal::total                 47204                       # number of callpals executed
system.cpu1.kern.mode_switch::kernel             1142                       # number of protection mode switches
system.cpu1.kern.mode_switch::user                492                       # number of protection mode switches
system.cpu1.kern.mode_switch::idle               2462                       # number of protection mode switches
system.cpu1.kern.mode_good::kernel                761                      
system.cpu1.kern.mode_good::user                  492                      
system.cpu1.kern.mode_good::idle                  269                      
system.cpu1.kern.mode_switch_good::kernel     0.666375                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle      0.109261                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total     1.775636                       # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel       35491661500      1.87%      1.87% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user           858235500      0.05%      1.91% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle        1862377378000     98.09%    100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context                     872                       # number of times the context was actually changed

---------- End Simulation Statistics   ----------