path: root/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.897529                       # Number of seconds simulated
sim_ticks                                1897528709500                       # Number of ticks simulated
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 133002                       # Simulator instruction rate (inst/s)
host_tick_rate                             4420145385                       # Simulator tick rate (ticks/s)
host_mem_usage                                 318652                       # Number of bytes of host memory used
host_seconds                                   429.29                       # Real time elapsed on the host
sim_insts                                    57096369                       # Number of instructions simulated
system.l2c.replacements                        396849                       # number of replacements
system.l2c.tagsinuse                     35842.640466                       # Cycle average of tags in use
system.l2c.total_refs                         2454377                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        435040                       # Sample count of references to valid blocks.
system.l2c.avg_refs                          5.641727                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                    9253572000                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::0                 12439.136290                       # Average occupied blocks per context
system.l2c.occ_blocks::1                   328.499708                       # Average occupied blocks per context
system.l2c.occ_blocks::2                 23075.004468                       # Average occupied blocks per context
system.l2c.occ_percent::0                    0.189806                       # Average percentage of cache occupancy
system.l2c.occ_percent::1                    0.005013                       # Average percentage of cache occupancy
system.l2c.occ_percent::2                    0.352097                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::0                    1462245                       # number of ReadReq hits
system.l2c.ReadReq_hits::1                     390216                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1852461                       # number of ReadReq hits
system.l2c.Writeback_hits::0                   805889                       # number of Writeback hits
system.l2c.Writeback_hits::total               805889                       # number of Writeback hits
system.l2c.UpgradeReq_hits::0                     158                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::1                     388                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 546                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::0                    42                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::1                    29                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                71                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::0                   131406                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::1                    39589                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               170995                       # number of ReadExReq hits
system.l2c.demand_hits::0                     1593651                       # number of demand (read+write) hits
system.l2c.demand_hits::1                      429805                       # number of demand (read+write) hits
system.l2c.demand_hits::2                           0                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2023456                       # number of demand (read+write) hits
system.l2c.overall_hits::0                    1593651                       # number of overall hits
system.l2c.overall_hits::1                     429805                       # number of overall hits
system.l2c.overall_hits::2                          0                       # number of overall hits
system.l2c.overall_hits::total                2023456                       # number of overall hits
system.l2c.ReadReq_misses::0                   304910                       # number of ReadReq misses
system.l2c.ReadReq_misses::1                     5378                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               310288                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::0                  2801                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::1                  1482                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              4283                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::0                 670                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::1                 687                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1357                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::0                 114075                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::1                  11670                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             125745                       # number of ReadExReq misses
system.l2c.demand_misses::0                    418985                       # number of demand (read+write) misses
system.l2c.demand_misses::1                     17048                       # number of demand (read+write) misses
system.l2c.demand_misses::2                         0                       # number of demand (read+write) misses
system.l2c.demand_misses::total                436033                       # number of demand (read+write) misses
system.l2c.overall_misses::0                   418985                       # number of overall misses
system.l2c.overall_misses::1                    17048                       # number of overall misses
system.l2c.overall_misses::2                        0                       # number of overall misses
system.l2c.overall_misses::total               436033                       # number of overall misses
system.l2c.ReadReq_miss_latency           16152594500                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency           19106500                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency          3089000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency          6595991500                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency            22748586000                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency           22748586000                       # number of overall miss cycles
system.l2c.ReadReq_accesses::0                1767155                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::1                 395594                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2162749                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::0               805889                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           805889                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::0                2959                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::1                1870                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            4829                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::0               712                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::1               716                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          1428                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::0               245481                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::1                51259                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           296740                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::0                 2012636                       # number of demand (read+write) accesses
system.l2c.demand_accesses::1                  446853                       # number of demand (read+write) accesses
system.l2c.demand_accesses::2                       0                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2459489                       # number of demand (read+write) accesses
system.l2c.overall_accesses::0                2012636                       # number of overall (read+write) accesses
system.l2c.overall_accesses::1                 446853                       # number of overall (read+write) accesses
system.l2c.overall_accesses::2                      0                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2459489                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::0              0.172543                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::1              0.013595                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::0           0.946604                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::1           0.792513                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::0         0.941011                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::1         0.959497                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::0            0.464700                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::1            0.227667                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::0               0.208177                       # miss rate for demand accesses
system.l2c.demand_miss_rate::1               0.038151                       # miss rate for demand accesses
system.l2c.demand_miss_rate::2               no_value                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           no_value                       # miss rate for demand accesses
system.l2c.overall_miss_rate::0              0.208177                       # miss rate for overall accesses
system.l2c.overall_miss_rate::1              0.038151                       # miss rate for overall accesses
system.l2c.overall_miss_rate::2              no_value                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          no_value                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::0   52974.958184                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::1   3003457.512086                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::2            inf                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::0  6821.313816                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::1 12892.375169                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::2          inf                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::0  4610.447761                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::1  4496.360990                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::2          inf                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total          inf                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::0 57821.534078                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::1 565209.211654                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::2          inf                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::0    54294.511737                       # average overall miss latency
system.l2c.demand_avg_miss_latency::1    1334384.443923                       # average overall miss latency
system.l2c.demand_avg_miss_latency::2             inf                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.l2c.overall_avg_miss_latency::0   54294.511737                       # average overall miss latency
system.l2c.overall_avg_miss_latency::1   1334384.443923                       # average overall miss latency
system.l2c.overall_avg_miss_latency::2            inf                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks                          121454                       # number of writebacks
system.l2c.ReadReq_mshr_hits                       17                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits                        17                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits                       17                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses                 310271                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses                4283                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses              1357                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses               125745                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses                  436016                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses                 436016                       # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency      12421352000                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency     171391500                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency     54292500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency     5066425000                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency       17487777000                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency      17487777000                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency    838216000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency   1556318498                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency   2394534498                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::0         0.175577                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::1         0.784317                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::2              inf                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::0      1.447448                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::1      2.290374                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::2           inf                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::0     1.905899                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::1     1.895251                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::2          inf                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::0       0.512239                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::1       2.453130                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::2            inf                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::0          0.216639                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::1          0.975748                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::2               inf                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total           inf                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::0         0.216639                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::1         0.975748                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::2              inf                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency 40033.880060                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency 40016.693906                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40009.211496                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency 40291.264066                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency  40108.108418                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency 40108.108418                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.iocache.replacements                     41698                       # number of replacements
system.iocache.tagsinuse                     0.465119                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                     41714                       # Sample count of references to valid blocks.
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.warmup_cycle              1708345431000                       # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::1                 0.465119                       # Average occupied blocks per context
system.iocache.occ_percent::1                0.029070                       # Average percentage of cache occupancy
system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
system.iocache.overall_hits::0                      0                       # number of overall hits
system.iocache.overall_hits::1                      0                       # number of overall hits
system.iocache.overall_hits::total                  0                       # number of overall hits
system.iocache.ReadReq_misses::1                  178                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              178                       # number of ReadReq misses
system.iocache.WriteReq_misses::1               41552                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
system.iocache.demand_misses::1                 41730                       # number of demand (read+write) misses
system.iocache.demand_misses::total             41730                       # number of demand (read+write) misses
system.iocache.overall_misses::0                    0                       # number of overall misses
system.iocache.overall_misses::1                41730                       # number of overall misses
system.iocache.overall_misses::total            41730                       # number of overall misses
system.iocache.ReadReq_miss_latency          20503998                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency       5720495806                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency         5740999804                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency        5740999804                       # number of overall miss cycles
system.iocache.ReadReq_accesses::1                178                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            178                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::1             41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
system.iocache.demand_accesses::1               41730                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           41730                       # number of demand (read+write) accesses
system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
system.iocache.overall_accesses::1              41730                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          41730                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::1                 1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::1                1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
system.iocache.demand_miss_rate::1                  1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
system.iocache.overall_miss_rate::1                 1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::1       115191                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::0          inf                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::1 137670.769301                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::0          inf                       # average overall miss latency
system.iocache.demand_avg_miss_latency::1 137574.881476                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.iocache.overall_avg_miss_latency::0          inf                       # average overall miss latency
system.iocache.overall_avg_miss_latency::1 137574.881476                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs      64616068                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                10458                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs  6178.625741                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks                       41520                       # number of writebacks
system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
system.iocache.ReadReq_mshr_misses                178                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses             41552                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses               41730                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses              41730                       # number of overall MSHR misses
system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.iocache.ReadReq_mshr_miss_latency     11247998                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency   3559637996                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency    3570885994                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency   3570885994                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::1            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::0          inf                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::1            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::0           inf                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::1             1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::1            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency        63191                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency 85667.067674                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency 85571.195639                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency 85571.195639                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.cpu0.dtb.fetch_hits                          0                       # ITB hits
system.cpu0.dtb.fetch_misses                        0                       # ITB misses
system.cpu0.dtb.fetch_acv                           0                       # ITB acv
system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu0.dtb.read_hits                     8560359                       # DTB read hits
system.cpu0.dtb.read_misses                     29048                       # DTB read misses
system.cpu0.dtb.read_acv                          513                       # DTB read access violations
system.cpu0.dtb.read_accesses                  619639                       # DTB read accesses
system.cpu0.dtb.write_hits                    5419292                       # DTB write hits
system.cpu0.dtb.write_misses                     5351                       # DTB write misses
system.cpu0.dtb.write_acv                         235                       # DTB write access violations
system.cpu0.dtb.write_accesses                 205704                       # DTB write accesses
system.cpu0.dtb.data_hits                    13979651                       # DTB hits
system.cpu0.dtb.data_misses                     34399                       # DTB misses
system.cpu0.dtb.data_acv                          748                       # DTB access violations
system.cpu0.dtb.data_accesses                  825343                       # DTB accesses
system.cpu0.itb.fetch_hits                     968518                       # ITB hits
system.cpu0.itb.fetch_misses                    28074                       # ITB misses
system.cpu0.itb.fetch_acv                         865                       # ITB acv
system.cpu0.itb.fetch_accesses                 996592                       # ITB accesses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.read_acv                            0                       # DTB read access violations
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.write_acv                           0                       # DTB write access violations
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.data_hits                           0                       # DTB hits
system.cpu0.itb.data_misses                         0                       # DTB misses
system.cpu0.itb.data_acv                            0                       # DTB access violations
system.cpu0.itb.data_accesses                       0                       # DTB accesses
system.cpu0.numCycles                       103762975                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.BPredUnit.lookups                12289120                       # Number of BP lookups
system.cpu0.BPredUnit.condPredicted          10322639                       # Number of conditional branches predicted
system.cpu0.BPredUnit.condIncorrect            425623                       # Number of conditional branches incorrect
system.cpu0.BPredUnit.BTBLookups             11096319                       # Number of BTB lookups
system.cpu0.BPredUnit.BTBHits                 5846860                       # Number of BTB hits
system.cpu0.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.BPredUnit.usedRAS                  811980                       # Number of times the RAS was used to get a target.
system.cpu0.BPredUnit.RASInCorrect              29936                       # Number of incorrect RAS predictions.
system.cpu0.fetch.icacheStallCycles          23947551                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                      63604775                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                   12289120                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches           6658840                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                     12410125                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                1977970                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.BlockedCycles              32452881                       # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles               32113                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles       186103                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       333368                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles           97                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                  7852316                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               261746                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.rateDist::samples          70661432                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             0.900134                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.212081                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                58251307     82.44%     82.44% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                  861864      1.22%     83.66% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                 1790389      2.53%     86.19% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                  838279      1.19%     87.38% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                 2691367      3.81%     91.19% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                  597435      0.85%     92.03% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                  679704      0.96%     92.99% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                  792267      1.12%     94.11% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 4158820      5.89%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total            70661432                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.118435                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.612981                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                25283379                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             31920291                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                 11354348                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles               836358                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               1267055                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved              507127                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred                32392                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              62175948                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts                94044                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               1267055                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                26303467                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles               12206310                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      16544701                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                 10563376                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles              3776521                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              58802666                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                 6783                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents                552005                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents              1306234                       # Number of times rename has blocked due to LSQ full
system.cpu0.rename.RenamedOperands           39659853                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups             71942390                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups        71601283                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups           341107                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             33288864                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                 6370981                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts           1352745                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts        204336                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                 10335573                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads             9033738                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores            5759436                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1575901                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         1714897                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  51649014                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded            1711174                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 50034185                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued            62931                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined        7150176                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined      3852149                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved       1166094                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples     70661432                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.708083                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.331294                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           48300171     68.35%     68.35% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1            9930839     14.05%     82.41% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            4875287      6.90%     89.31% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            3134712      4.44%     93.74% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            2288875      3.24%     96.98% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5            1259030      1.78%     98.77% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6             656858      0.93%     99.69% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             168442      0.24%     99.93% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8              47218      0.07%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total       70661432                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                  64961     14.10%     14.10% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     0      0.00%     14.10% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%     14.10% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     14.10% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     14.10% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     14.10% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     14.10% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     14.10% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     14.10% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     14.10% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     14.10% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     14.10% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     14.10% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     14.10% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     14.10% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     14.10% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     14.10% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     14.10% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     14.10% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     14.10% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     14.10% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     14.10% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     14.10% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     14.10% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     14.10% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     14.10% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     14.10% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     14.10% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     14.10% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                248589     53.97%     68.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               147038     31.92%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass             3305      0.01%      0.01% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             34793099     69.54%     69.55% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               56077      0.11%     69.66% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     69.66% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd              13836      0.03%     69.68% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     69.68% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     69.68% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     69.68% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv               1652      0.00%     69.69% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     69.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     69.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     69.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     69.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     69.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     69.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     69.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     69.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     69.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     69.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     69.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     69.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     69.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     69.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     69.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     69.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     69.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     69.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     69.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     69.69% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead             8926243     17.84%     87.53% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite            5486267     10.97%     98.49% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess            753706      1.51%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              50034185                       # Type of FU issued
system.cpu0.iq.rate                          0.482197                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                     460588                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.009205                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         170766492                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         60297186                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     48772869                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads             486828                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes            236130                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses       232978                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              50238035                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                 253433                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          485739                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      1334836                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses        17971                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        25456                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores       519571                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads        18977                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked       164713                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               1267055                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                8486951                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles               577503                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           56521315                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts           733695                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts              9033738                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts             5759436                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts           1510903                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                459190                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                 7711                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         25456                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        319028                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       300441                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              619469                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             49457194                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts              8612039                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           576990                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                      3161127                       # number of nop insts executed
system.cpu0.iew.exec_refs                    14049434                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                 7908844                       # Number of branches executed
system.cpu0.iew.exec_stores                   5437395                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.476636                       # Inst execution rate
system.cpu0.iew.wb_sent                      49114578                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     49005847                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 24510505                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 32850763                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.472286                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.746117                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitCommittedInsts      48687390                       # The number of committed instructions
system.cpu0.commit.commitSquashedInsts        7735637                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls         545080                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           563607                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples     69394377                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.701604                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.587762                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     50596179     72.91%     72.91% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1      7970613     11.49%     84.40% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      4358860      6.28%     90.68% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      2336816      3.37%     94.05% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4      1278043      1.84%     95.89% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       512868      0.74%     96.63% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6       404165      0.58%     97.21% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       607557      0.88%     98.08% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1329276      1.92%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total     69394377                       # Number of insts commited each cycle
system.cpu0.commit.count                     48687390                       # Number of instructions committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      12938767                       # Number of memory references committed
system.cpu0.commit.loads                      7698902                       # Number of loads committed
system.cpu0.commit.membars                     184242                       # Number of memory barriers committed
system.cpu0.commit.branches                   7372386                       # Number of branches committed
system.cpu0.commit.fp_insts                    230446                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 45102183                       # Number of committed integer instructions.
system.cpu0.commit.function_calls              618802                       # Number of function calls committed.
system.cpu0.commit.bw_lim_events              1329276                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                   124302463                       # The number of ROB reads
system.cpu0.rob.rob_writes                  114114055                       # The number of ROB writes
system.cpu0.timesIdled                        1107408                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                       33101543                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.committedInsts                   45891664                       # Number of Instructions Simulated
system.cpu0.committedInsts_total             45891664                       # Number of Instructions Simulated
system.cpu0.cpi                              2.261042                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        2.261042                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.442274                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.442274                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads                65164143                       # number of integer regfile reads
system.cpu0.int_regfile_writes               35661718                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                   113503                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                  115176                       # number of floating regfile writes
system.cpu0.misc_regfile_reads                1562482                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                761048                       # number of misc regfile writes
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi         no_value                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle      no_value                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk        no_value                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc      no_value                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk        no_value                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle      no_value                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc      no_value                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn       no_value                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal       no_value                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.cpu0.icache.replacements                795450                       # number of replacements
system.cpu0.icache.tagsinuse               509.996584                       # Cycle average of tags in use
system.cpu0.icache.total_refs                 7012391                       # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs                795959                       # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs                  8.809990                       # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle           23368345000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::0           509.996584                       # Average occupied blocks per context
system.cpu0.icache.occ_percent::0            0.996087                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::0            7012391                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total        7012391                       # number of ReadReq hits
system.cpu0.icache.demand_hits::0             7012391                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::1                   0                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total         7012391                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::0            7012391                       # number of overall hits
system.cpu0.icache.overall_hits::1                  0                       # number of overall hits
system.cpu0.icache.overall_hits::total        7012391                       # number of overall hits
system.cpu0.icache.ReadReq_misses::0           839924                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       839924                       # number of ReadReq misses
system.cpu0.icache.demand_misses::0            839924                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::1                 0                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        839924                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::0           839924                       # number of overall misses
system.cpu0.icache.overall_misses::1                0                       # number of overall misses
system.cpu0.icache.overall_misses::total       839924                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency   12708309496                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency    12708309496                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency   12708309496                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::0        7852315                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total      7852315                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::0         7852315                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total      7852315                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::0        7852315                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total      7852315                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::0      0.106965                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::0       0.106965                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::0      0.106965                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::0 15130.308809                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::0 15130.308809                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::0 15130.308809                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs      1208998                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              102                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 11852.921569                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.writebacks                     234                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits            43832                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits             43832                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits            43832                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses         796092                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses          796092                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses         796092                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency   9657065498                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency   9657065498                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency   9657065498                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::0     0.101383                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::0     0.101383                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::0     0.101383                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12130.589804                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency 12130.589804                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency 12130.589804                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.replacements               1219575                       # number of replacements
system.cpu0.dcache.tagsinuse               498.032464                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                10118125                       # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs               1220087                       # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs                  8.292954                       # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::0           499.032464                       # Average occupied blocks per context
system.cpu0.dcache.occ_blocks::1            -1.000000                       # Average occupied blocks per context
system.cpu0.dcache.occ_percent::0            0.974673                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::1           -0.001953                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::0            6334107                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        6334107                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::0           3441361                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       3441361                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::0       153669                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       153669                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::0        174688                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       174688                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::0             9775468                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total         9775468                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::0            9775468                       # number of overall hits
system.cpu0.dcache.overall_hits::1                  0                       # number of overall hits
system.cpu0.dcache.overall_hits::total        9775468                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::0          1480500                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      1480500                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::0         1604462                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1604462                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::0        19020                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        19020                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::0         4294                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total         4294                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::0           3084962                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       3084962                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::0          3084962                       # number of overall misses
system.cpu0.dcache.overall_misses::1                0                       # number of overall misses
system.cpu0.dcache.overall_misses::total      3084962                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency   34097804500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency  52119525554                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency    280406500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency     58991000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency    86217330054                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency   86217330054                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::0        7814607                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      7814607                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::0       5045823                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      5045823                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::0       172689                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       172689                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::0       178982                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       178982                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::0        12860430                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     12860430                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::0       12860430                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     12860430                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::0      0.189453                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::0     0.317978                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::0     0.110140                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::0     0.023991                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::0       0.239880                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::0      0.239880                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::0 23031.276258                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::0 32484.113400                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 14742.718191                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 13738.006521                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::0 27947.614931                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::0 27947.614931                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs    874274400                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets       238500                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs            96465                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets             10                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs  9063.125486                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets        23850                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks                  701727                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits           509168                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits         1351881                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits         4474                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits           1861049                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits          1861049                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses         971332                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses        252581                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses        14546                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses         4294                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses         1223913                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses        1223913                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency  23290479000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency   7870556900                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency    149366500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency     46100000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency  31161035900                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency  31161035900                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency    917406500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency   1329367998                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency   2246774498                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::0     0.124297                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::0     0.050057                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0     0.084232                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0     0.023991                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::0     0.095169                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::0     0.095169                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23977.876771                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 31160.526326                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 10268.561804                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 10735.910573                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency 25460.172333                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency 25460.172333                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits                          0                       # ITB hits
system.cpu1.dtb.fetch_misses                        0                       # ITB misses
system.cpu1.dtb.fetch_acv                           0                       # ITB acv
system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu1.dtb.read_hits                     2434396                       # DTB read hits
system.cpu1.dtb.read_misses                     12632                       # DTB read misses
system.cpu1.dtb.read_acv                           51                       # DTB read access violations
system.cpu1.dtb.read_accesses                  349555                       # DTB read accesses
system.cpu1.dtb.write_hits                    1633702                       # DTB write hits
system.cpu1.dtb.write_misses                     3988                       # DTB write misses
system.cpu1.dtb.write_acv                          91                       # DTB write access violations
system.cpu1.dtb.write_accesses                 134749                       # DTB write accesses
system.cpu1.dtb.data_hits                     4068098                       # DTB hits
system.cpu1.dtb.data_misses                     16620                       # DTB misses
system.cpu1.dtb.data_acv                          142                       # DTB access violations
system.cpu1.dtb.data_accesses                  484304                       # DTB accesses
system.cpu1.itb.fetch_hits                     488641                       # ITB hits
system.cpu1.itb.fetch_misses                     8868                       # ITB misses
system.cpu1.itb.fetch_acv                         207                       # ITB acv
system.cpu1.itb.fetch_accesses                 497509                       # ITB accesses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.read_acv                            0                       # DTB read access violations
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.write_acv                           0                       # DTB write access violations
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.data_hits                           0                       # DTB hits
system.cpu1.itb.data_misses                         0                       # DTB misses
system.cpu1.itb.data_acv                            0                       # DTB access violations
system.cpu1.itb.data_accesses                       0                       # DTB accesses
system.cpu1.numCycles                        20348668                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.BPredUnit.lookups                 3352403                       # Number of BP lookups
system.cpu1.BPredUnit.condPredicted           2780204                       # Number of conditional branches predicted
system.cpu1.BPredUnit.condIncorrect            112990                       # Number of conditional branches incorrect
system.cpu1.BPredUnit.BTBLookups              3035961                       # Number of BTB lookups
system.cpu1.BPredUnit.BTBHits                 1319312                       # Number of BTB hits
system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.BPredUnit.usedRAS                  232566                       # Number of times the RAS was used to get a target.
system.cpu1.BPredUnit.RASInCorrect               9070                       # Number of incorrect RAS predictions.
system.cpu1.fetch.icacheStallCycles           8042198                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                      15968682                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                    3352403                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches           1551878                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                      2969461                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                 549599                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.BlockedCycles               7368633                       # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles               27992                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles        74441                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles        61172                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles           29                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                  1904129                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes                71381                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples          18894151                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             0.845165                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.201588                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                15924690     84.28%     84.28% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                  239855      1.27%     85.55% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                  362060      1.92%     87.47% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                  226098      1.20%     88.67% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                  430016      2.28%     90.94% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                  142596      0.75%     91.70% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                  181045      0.96%     92.65% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                  295229      1.56%     94.22% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                 1092562      5.78%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total            18894151                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.164748                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.784753                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                 7867478                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles              7772170                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                  2762632                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles               150042                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles                341828                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved              143049                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred                 8486                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              15583049                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts                23483                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles                341828                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                 8134306                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                 601370                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles       6389331                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                  2635739                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles               791575                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              14485157                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                  185                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                 55864                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents               183661                       # Number of times rename has blocked due to LSQ full
system.cpu1.rename.RenamedOperands            9468885                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups             17315691                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups        17110872                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups           204819                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps              7931339                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                 1537546                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts            569619                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts         61560                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                  2500740                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads             2578124                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores            1732920                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads           321113                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores          190156                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                  12582391                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded             647000                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                 12202318                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued            26509                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined        1926210                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined      1020296                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        460997                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples     18894151                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.645825                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.311169                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0           13531447     71.62%     71.62% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1            2408615     12.75%     84.37% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2            1089992      5.77%     90.13% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3             719494      3.81%     93.94% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4             600531      3.18%     97.12% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5             311690      1.65%     98.77% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6             155684      0.82%     99.59% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7              53025      0.28%     99.87% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8              23673      0.13%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total       18894151                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                   4502      1.97%      1.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     0      0.00%      1.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      1.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      1.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      1.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      1.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      1.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      1.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      1.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      1.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      1.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      1.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      1.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      1.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      1.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      1.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      1.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      1.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      1.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      1.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      1.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      1.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      1.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      1.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      1.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      1.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      1.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      1.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      1.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                121874     53.21%     55.17% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite               102674     44.83%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass             3982      0.03%      0.03% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu              7613703     62.40%     62.43% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               19536      0.16%     62.59% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     62.59% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd              13122      0.11%     62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv               1991      0.02%     62.71% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     62.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     62.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     62.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     62.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     62.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     62.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     62.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     62.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     62.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     62.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     62.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     62.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     62.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     62.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     62.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     62.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     62.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     62.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     62.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     62.71% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead             2552683     20.92%     83.63% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite            1661486     13.62%     97.25% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess            335815      2.75%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total              12202318                       # Type of FU issued
system.cpu1.iq.rate                          0.599662                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                     229050                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.018771                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads          43260661                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         15016823                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses     11811979                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads             293685                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes            142362                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses       139746                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses              12273711                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                 153675                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads          108256                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads       372523                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses         7917                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation         4307                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores       156502                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads          333                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked        28285                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles                341828                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                 445544                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles                34164                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           13910925                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts           201807                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts              2578124                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts             1732920                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            582063                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                 21599                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                 6281                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents          4307                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect         78974                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect       111447                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              190421                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts             12072034                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts              2457890                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts           130284                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       681534                       # number of nop insts executed
system.cpu1.iew.exec_refs                     4103399                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                 1804932                       # Number of branches executed
system.cpu1.iew.exec_stores                   1645509                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.593259                       # Inst execution rate
system.cpu1.iew.wb_sent                      11986744                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                     11951725                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                  5550831                       # num instructions producing a value
system.cpu1.iew.wb_consumers                  7770927                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.587347                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.714307                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitCommittedInsts      11805751                       # The number of committed instructions
system.cpu1.commit.commitSquashedInsts        2024872                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls         186003                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           175934                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples     18552323                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.636349                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.571810                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     14118650     76.10%     76.10% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1      2051209     11.06%     87.16% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2       792595      4.27%     91.43% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3       477671      2.57%     94.01% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4       327821      1.77%     95.77% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5       149583      0.81%     96.58% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6       116875      0.63%     97.21% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7       167462      0.90%     98.11% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8       350457      1.89%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total     18552323                       # Number of insts commited each cycle
system.cpu1.commit.count                     11805751                       # Number of instructions committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                       3782019                       # Number of memory references committed
system.cpu1.commit.loads                      2205601                       # Number of loads committed
system.cpu1.commit.membars                      61380                       # Number of memory barriers committed
system.cpu1.commit.branches                   1685692                       # Number of branches committed
system.cpu1.commit.fp_insts                    138212                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                 10911872                       # Number of committed integer instructions.
system.cpu1.commit.function_calls              184868                       # Number of function calls committed.
system.cpu1.commit.bw_lim_events               350457                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                    31928567                       # The number of ROB reads
system.cpu1.rob.rob_writes                   28001823                       # The number of ROB writes
system.cpu1.timesIdled                         205057                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                        1454517                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.committedInsts                   11204705                       # Number of Instructions Simulated
system.cpu1.committedInsts_total             11204705                       # Number of Instructions Simulated
system.cpu1.cpi                              1.816082                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.816082                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.550636                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.550636                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                15543323                       # number of integer regfile reads
system.cpu1.int_regfile_writes                8446180                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                    74822                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                   74815                       # number of floating regfile writes
system.cpu1.misc_regfile_reads                 675670                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                285692                       # number of misc regfile writes
system.cpu1.icache.replacements                294345                       # number of replacements
system.cpu1.icache.tagsinuse               471.340417                       # Cycle average of tags in use
system.cpu1.icache.total_refs                 1598818                       # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs                294856                       # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs                  5.422369                       # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle          1874432600000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::0           471.340417                       # Average occupied blocks per context
system.cpu1.icache.occ_percent::0            0.920587                       # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::0            1598818                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total        1598818                       # number of ReadReq hits
system.cpu1.icache.demand_hits::0             1598818                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::1                   0                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total         1598818                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::0            1598818                       # number of overall hits
system.cpu1.icache.overall_hits::1                  0                       # number of overall hits
system.cpu1.icache.overall_hits::total        1598818                       # number of overall hits
system.cpu1.icache.ReadReq_misses::0           305311                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       305311                       # number of ReadReq misses
system.cpu1.icache.demand_misses::0            305311                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::1                 0                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        305311                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::0           305311                       # number of overall misses
system.cpu1.icache.overall_misses::1                0                       # number of overall misses
system.cpu1.icache.overall_misses::total       305311                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency    4483412500                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency     4483412500                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency    4483412500                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::0        1904129                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total      1904129                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::0         1904129                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total      1904129                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::0        1904129                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total      1904129                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::0      0.160342                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::0       0.160342                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::0      0.160342                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::0 14684.739495                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::0 14684.739495                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::0 14684.739495                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs       116500                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs               18                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs  6472.222222                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.writebacks                      49                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_hits            10391                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits             10391                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits            10391                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses         294920                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses          294920                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses         294920                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency   3431981500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency   3431981500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency   3431981500                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::0     0.154884                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::0     0.154884                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::0     0.154884                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11636.991387                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency 11636.991387                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency 11636.991387                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.replacements                154143                       # number of replacements
system.cpu1.dcache.tagsinuse               476.574727                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                 3264047                       # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs                154464                       # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs                 21.131442                       # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle          1874646667000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::0           476.574727                       # Average occupied blocks per context
system.cpu1.dcache.occ_percent::0            0.930810                       # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::0            1976745                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        1976745                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::0           1193181                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       1193181                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::0        47069                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        47069                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::0         45973                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        45973                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::0             3169926                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         3169926                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::0            3169926                       # number of overall hits
system.cpu1.dcache.overall_hits::1                  0                       # number of overall hits
system.cpu1.dcache.overall_hits::total        3169926                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::0           282407                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       282407                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::0          325995                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       325995                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::0         7824                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total         7824                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::0         4577                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total         4577                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::0            608402                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        608402                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::0           608402                       # number of overall misses
system.cpu1.dcache.overall_misses::1                0                       # number of overall misses
system.cpu1.dcache.overall_misses::total       608402                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency    4155262000                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency   7647875941                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency     85879000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency     62313500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency    11803137941                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency   11803137941                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::0        2259152                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      2259152                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::0       1519176                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      1519176                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::0        54893                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        54893                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::0        50550                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        50550                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::0         3778328                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      3778328                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::0        3778328                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      3778328                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::0      0.125006                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::0     0.214587                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::0     0.142532                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::0     0.090544                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::0       0.161024                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::0      0.161024                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::0 14713.735849                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::0 23460.101968                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 10976.354806                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 13614.485471                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::0 19400.228699                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::0 19400.228699                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs     94033995                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs             7725                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12172.685437                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks                  103879                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits           174324                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits          267778                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits          757                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits            442102                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits           442102                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses         108083                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses         58217                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses         7067                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses         4577                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses          166300                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses         166300                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency   1297456000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency   1215847490                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency     55744000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency     48574500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency   2513303490                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency   2513303490                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency     18621500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency    393979500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency    412601000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::0     0.047842                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::0     0.038321                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0     0.128741                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0     0.090544                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::0     0.044014                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::0     0.044014                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12004.255988                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 20884.749987                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency  7887.929815                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 10612.737601                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency 15113.069693                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency 15113.069693                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    6679                       # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei                    170123                       # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0                   59613     40.27%     40.27% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21                    237      0.16%     40.44% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22                   1922      1.30%     41.73% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30                    309      0.21%     41.94% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31                  85934     58.06%    100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total              148015                       # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0                    58855     49.10%     49.10% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21                     237      0.20%     49.30% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22                    1922      1.60%     50.90% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30                     309      0.26%     51.16% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31                   58546     48.84%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total               119869                       # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0            1860434296000     98.05%     98.05% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21               90872000      0.00%     98.05% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22              391830000      0.02%     98.07% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30              123760000      0.01%     98.08% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31            36487097000      1.92%    100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total        1897527855000                       # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0                 0.987285                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31                0.681290                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2                         7      3.35%      3.35% # number of syscalls executed
system.cpu0.kern.syscall::3                        17      8.13%     11.48% # number of syscalls executed
system.cpu0.kern.syscall::4                         3      1.44%     12.92% # number of syscalls executed
system.cpu0.kern.syscall::6                        31     14.83%     27.75% # number of syscalls executed
system.cpu0.kern.syscall::12                        1      0.48%     28.23% # number of syscalls executed
system.cpu0.kern.syscall::17                        8      3.83%     32.06% # number of syscalls executed
system.cpu0.kern.syscall::19                        9      4.31%     36.36% # number of syscalls executed
system.cpu0.kern.syscall::20                        6      2.87%     39.23% # number of syscalls executed
system.cpu0.kern.syscall::23                        1      0.48%     39.71% # number of syscalls executed
system.cpu0.kern.syscall::24                        3      1.44%     41.15% # number of syscalls executed
system.cpu0.kern.syscall::33                        6      2.87%     44.02% # number of syscalls executed
system.cpu0.kern.syscall::41                        2      0.96%     44.98% # number of syscalls executed
system.cpu0.kern.syscall::45                       33     15.79%     60.77% # number of syscalls executed
system.cpu0.kern.syscall::47                        3      1.44%     62.20% # number of syscalls executed
system.cpu0.kern.syscall::48                        9      4.31%     66.51% # number of syscalls executed
system.cpu0.kern.syscall::54                       10      4.78%     71.29% # number of syscalls executed
system.cpu0.kern.syscall::58                        1      0.48%     71.77% # number of syscalls executed
system.cpu0.kern.syscall::59                        5      2.39%     74.16% # number of syscalls executed
system.cpu0.kern.syscall::71                       23     11.00%     85.17% # number of syscalls executed
system.cpu0.kern.syscall::73                        3      1.44%     86.60% # number of syscalls executed
system.cpu0.kern.syscall::74                        6      2.87%     89.47% # number of syscalls executed
system.cpu0.kern.syscall::87                        1      0.48%     89.95% # number of syscalls executed
system.cpu0.kern.syscall::90                        3      1.44%     91.39% # number of syscalls executed
system.cpu0.kern.syscall::92                        9      4.31%     95.69% # number of syscalls executed
system.cpu0.kern.syscall::97                        2      0.96%     96.65% # number of syscalls executed
system.cpu0.kern.syscall::98                        2      0.96%     97.61% # number of syscalls executed
system.cpu0.kern.syscall::132                       1      0.48%     98.09% # number of syscalls executed
system.cpu0.kern.syscall::144                       2      0.96%     99.04% # number of syscalls executed
system.cpu0.kern.syscall::147                       2      0.96%    100.00% # number of syscalls executed
system.cpu0.kern.syscall::total                   209                       # number of syscalls executed
system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::wripir                  406      0.26%      0.26% # number of callpals executed
system.cpu0.kern.callpal::wrmces                    1      0.00%      0.26% # number of callpals executed
system.cpu0.kern.callpal::wrfen                     1      0.00%      0.26% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.26% # number of callpals executed
system.cpu0.kern.callpal::swpctx                 3167      2.03%      2.29% # number of callpals executed
system.cpu0.kern.callpal::tbi                      45      0.03%      2.32% # number of callpals executed
system.cpu0.kern.callpal::wrent                     7      0.00%      2.33% # number of callpals executed
system.cpu0.kern.callpal::swpipl               141170     90.48%     92.80% # number of callpals executed
system.cpu0.kern.callpal::rdps                   6359      4.08%     96.88% # number of callpals executed
system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.88% # number of callpals executed
system.cpu0.kern.callpal::wrusp                     2      0.00%     96.88% # number of callpals executed
system.cpu0.kern.callpal::rdusp                     8      0.01%     96.89% # number of callpals executed
system.cpu0.kern.callpal::whami                     2      0.00%     96.89% # number of callpals executed
system.cpu0.kern.callpal::rti                    4376      2.80%     99.69% # number of callpals executed
system.cpu0.kern.callpal::callsys                 348      0.22%     99.91% # number of callpals executed
system.cpu0.kern.callpal::imb                     134      0.09%    100.00% # number of callpals executed
system.cpu0.kern.callpal::total                156029                       # number of callpals executed
system.cpu0.kern.mode_switch::kernel             6806                       # number of protection mode switches
system.cpu0.kern.mode_switch::user               1160                       # number of protection mode switches
system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
system.cpu0.kern.mode_good::kernel               1159                      
system.cpu0.kern.mode_good::user                 1160                      
system.cpu0.kern.mode_good::idle                    0                      
system.cpu0.kern.mode_switch_good::kernel     0.170291                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle      no_value                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total     no_value                       # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel      1895695413000     99.90%     99.90% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user          1832434000      0.10%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context                    3168                       # number of times the context was actually changed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2565                       # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei                     71341                       # number of hwrei instructions executed
system.cpu1.kern.ipl_count::0                   23380     38.18%     38.18% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22                   1920      3.14%     41.31% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30                    406      0.66%     41.98% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31                  35533     58.02%    100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total               61239                       # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0                    22761     47.98%     47.98% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22                    1920      4.05%     52.02% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30                     406      0.86%     52.88% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31                   22355     47.12%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total                47442                       # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0            1868516653000     98.47%     98.47% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22              343880500      0.02%     98.49% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30              155607500      0.01%     98.50% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31            28447585000      1.50%    100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total        1897463726000                       # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0                 0.973524                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::31                0.629133                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::2                         1      0.85%      0.85% # number of syscalls executed
system.cpu1.kern.syscall::3                        13     11.11%     11.97% # number of syscalls executed
system.cpu1.kern.syscall::4                         1      0.85%     12.82% # number of syscalls executed
system.cpu1.kern.syscall::6                        11      9.40%     22.22% # number of syscalls executed
system.cpu1.kern.syscall::15                        1      0.85%     23.08% # number of syscalls executed
system.cpu1.kern.syscall::17                        7      5.98%     29.06% # number of syscalls executed
system.cpu1.kern.syscall::19                        1      0.85%     29.91% # number of syscalls executed
system.cpu1.kern.syscall::23                        3      2.56%     32.48% # number of syscalls executed
system.cpu1.kern.syscall::24                        3      2.56%     35.04% # number of syscalls executed
system.cpu1.kern.syscall::33                        5      4.27%     39.32% # number of syscalls executed
system.cpu1.kern.syscall::45                       21     17.95%     57.26% # number of syscalls executed
system.cpu1.kern.syscall::47                        3      2.56%     59.83% # number of syscalls executed
system.cpu1.kern.syscall::48                        1      0.85%     60.68% # number of syscalls executed
system.cpu1.kern.syscall::59                        2      1.71%     62.39% # number of syscalls executed
system.cpu1.kern.syscall::71                       31     26.50%     88.89% # number of syscalls executed
system.cpu1.kern.syscall::74                       10      8.55%     97.44% # number of syscalls executed
system.cpu1.kern.syscall::132                       3      2.56%    100.00% # number of syscalls executed
system.cpu1.kern.syscall::total                   117                       # number of syscalls executed
system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu1.kern.callpal::wripir                  309      0.49%      0.49% # number of callpals executed
system.cpu1.kern.callpal::wrmces                    1      0.00%      0.49% # number of callpals executed
system.cpu1.kern.callpal::wrfen                     1      0.00%      0.49% # number of callpals executed
system.cpu1.kern.callpal::swpctx                 1667      2.62%      3.12% # number of callpals executed
system.cpu1.kern.callpal::tbi                       9      0.01%      3.13% # number of callpals executed
system.cpu1.kern.callpal::wrent                     7      0.01%      3.14% # number of callpals executed
system.cpu1.kern.callpal::swpipl                55390     87.20%     90.34% # number of callpals executed
system.cpu1.kern.callpal::rdps                   2392      3.77%     94.10% # number of callpals executed
system.cpu1.kern.callpal::wrkgp                     1      0.00%     94.10% # number of callpals executed
system.cpu1.kern.callpal::wrusp                     5      0.01%     94.11% # number of callpals executed
system.cpu1.kern.callpal::rdusp                     1      0.00%     94.11% # number of callpals executed
system.cpu1.kern.callpal::whami                     3      0.00%     94.12% # number of callpals executed
system.cpu1.kern.callpal::rti                    3522      5.54%     99.66% # number of callpals executed
system.cpu1.kern.callpal::callsys                 167      0.26%     99.92% # number of callpals executed
system.cpu1.kern.callpal::imb                      47      0.07%    100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
system.cpu1.kern.callpal::total                 63524                       # number of callpals executed
system.cpu1.kern.mode_switch::kernel             1934                       # number of protection mode switches
system.cpu1.kern.mode_switch::user                578                       # number of protection mode switches
system.cpu1.kern.mode_switch::idle               2650                       # number of protection mode switches
system.cpu1.kern.mode_good::kernel                909                      
system.cpu1.kern.mode_good::user                  578                      
system.cpu1.kern.mode_good::idle                  331                      
system.cpu1.kern.mode_switch_good::kernel     0.470010                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle      0.124906                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total     1.594916                       # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel        6826914500      0.36%      0.36% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user           949063500      0.05%      0.41% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle        1889043105000     99.59%    100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context                    1668                       # number of times the context was actually changed

---------- End Simulation Statistics   ----------