path: root/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
host_inst_rate                                 158375                       # Simulator instruction rate (inst/s)
host_mem_usage                                 283016                       # Number of bytes of host memory used
host_seconds                                   359.78                       # Real time elapsed on the host
host_tick_rate                             5283356726                       # Simulator tick rate (ticks/s)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                    56979511                       # Number of instructions simulated
sim_seconds                                  1.900829                       # Number of seconds simulated
sim_ticks                                1900828642500                       # Number of ticks simulated
system.cpu0.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.BPredUnit.BTBHits                 5876227                       # Number of BTB hits
system.cpu0.BPredUnit.BTBLookups             11175399                       # Number of BTB lookups
system.cpu0.BPredUnit.RASInCorrect              27772                       # Number of incorrect RAS predictions.
system.cpu0.BPredUnit.condIncorrect            686228                       # Number of conditional branches incorrect
system.cpu0.BPredUnit.condPredicted          10431445                       # Number of conditional branches predicted
system.cpu0.BPredUnit.lookups                12491766                       # Number of BP lookups
system.cpu0.BPredUnit.usedRAS                  881103                       # Number of times the RAS was used to get a target.
system.cpu0.commit.COM:branches               7527502                       # Number of branches committed
system.cpu0.commit.COM:bw_lim_events           920717                       # number cycles where commit BW limit reached
system.cpu0.commit.COM:bw_limited                   0                       # number of insts not committed due to BW limits
system.cpu0.commit.COM:committed_per_cycle::samples     78591026                       # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::mean     0.633671                       # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::stdev     1.400615                       # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::0     57312142     72.92%     72.92% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::1      9330889     11.87%     84.80% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::2      5427191      6.91%     91.70% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::3      2440699      3.11%     94.81% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::4      1862016      2.37%     97.18% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::5       630346      0.80%     97.98% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::6       341230      0.43%     98.41% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::7       325796      0.41%     98.83% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::8       920717      1.17%    100.00% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::total     78591026                       # Number of insts commited each cycle
system.cpu0.commit.COM:count                 49800850                       # Number of instructions committed
system.cpu0.commit.COM:loads                  8090667                       # Number of loads committed
system.cpu0.commit.COM:membars                 191655                       # Number of memory barriers committed
system.cpu0.commit.COM:refs                  13515444                       # Number of memory references committed
system.cpu0.commit.COM:swp_count                    0                       # Number of s/w prefetches committed
system.cpu0.commit.branchMispredicts           653618                       # The number of times a branch was mispredicted
system.cpu0.commit.commitCommittedInsts      49800850                       # The number of committed instructions
system.cpu0.commit.commitNonSpecStalls         564747                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.commitSquashedInsts        7272798                       # The number of squashed insts skipped by commit
system.cpu0.committedInsts                   46939821                       # Number of Instructions Simulated
system.cpu0.committedInsts_total             46939821                       # Number of Instructions Simulated
system.cpu0.cpi                              2.403302                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        2.403302                       # CPI: Total CPI of All Threads
system.cpu0.dcache.LoadLockedReq_accesses::0       178200                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       178200                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 14347.227969                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 10538.474362                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_hits::0       158864                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       158864                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_miss_latency    277418000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_rate::0     0.108507                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_misses::0        19336                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        19336                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_mshr_hits         4339                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency    158045500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0     0.084158                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_misses        14997                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.ReadReq_accesses::0        8021076                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      8021076                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_avg_miss_latency::0 23752.144269                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23767.790910                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_hits::0            6644033                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        6644033                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_miss_latency   32707724000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_rate::0      0.171678                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_misses::0          1377043                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      1377043                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_mshr_hits           391877                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_miss_latency  23415219500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::0     0.122822                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_misses         985166                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency    920846500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.StoreCondReq_accesses::0       185095                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       185095                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 13168.588688                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 10165.293795                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_hits::0        181453                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       181453                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_miss_latency     47960000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_rate::0     0.019676                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_misses::0         3642                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total         3642                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_mshr_miss_latency     37022000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0     0.019676                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_misses         3642                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.WriteReq_accesses::0       5224623                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      5224623                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_avg_miss_latency::0 32385.164412                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 30570.974366                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_hits::0           3608317                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       3608317                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_miss_latency  52344335550                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_rate::0     0.309363                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_misses::0         1616306                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1616306                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_mshr_hits         1352902                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_miss_latency   8052516932                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_rate::0     0.050416                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_misses        263404                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency   1320254998                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.avg_blocked_cycles::no_mshrs  8777.270227                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 21937.500000                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_refs                  8.502455                       # Average number of references to valid blocks.
system.cpu0.dcache.blocked::no_mshrs            83541                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              8                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_mshrs    733261932                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets       175500                       # number of cycles access was blocked
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.demand_accesses::0        13245699                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     13245699                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_avg_miss_latency::0 28413.679644                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency 25203.021402                       # average overall mshr miss latency
system.cpu0.dcache.demand_hits::0            10252350                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        10252350                       # number of demand (read+write) hits
system.cpu0.dcache.demand_miss_latency    85052059550                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_rate::0       0.225986                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu0.dcache.demand_misses::0           2993349                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       2993349                       # number of demand (read+write) misses
system.cpu0.dcache.demand_mshr_hits           1744779                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_miss_latency  31467736432                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_rate::0     0.094262                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_misses         1248570                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.occ_%::0                  0.973042                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_%::1                 -0.001953                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_blocks::0           498.197480                       # Average occupied blocks per context
system.cpu0.dcache.occ_blocks::1            -1.000000                       # Average occupied blocks per context
system.cpu0.dcache.overall_accesses::0       13245699                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     13245699                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_avg_miss_latency::0 28413.679644                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency 25203.021402                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_hits::0           10252350                       # number of overall hits
system.cpu0.dcache.overall_hits::1                  0                       # number of overall hits
system.cpu0.dcache.overall_hits::total       10252350                       # number of overall hits
system.cpu0.dcache.overall_miss_latency   85052059550                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_rate::0      0.225986                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu0.dcache.overall_misses::0          2993349                       # number of overall misses
system.cpu0.dcache.overall_misses::1                0                       # number of overall misses
system.cpu0.dcache.overall_misses::total      2993349                       # number of overall misses
system.cpu0.dcache.overall_mshr_hits          1744779                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_miss_latency  31467736432                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_rate::0     0.094262                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_misses        1248570                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_uncacheable_latency   2241101498                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.replacements               1246736                       # number of replacements
system.cpu0.dcache.sampled_refs               1247248                       # Sample count of references to valid blocks.
system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu0.dcache.tagsinuse               497.197481                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                10604670                       # Total number of references to valid blocks.
system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.writebacks                  721609                       # number of writebacks
system.cpu0.decode.DECODE:BlockedCycles      34091757                       # Number of cycles decode is blocked
system.cpu0.decode.DECODE:BranchMispred         33333                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DECODE:BranchResolved       521194                       # Number of times decode resolved a branch
system.cpu0.decode.DECODE:DecodedInsts       62604059                       # Number of instructions handled by decode
system.cpu0.decode.DECODE:IdleCycles         32208044                       # Number of cycles decode is idle
system.cpu0.decode.DECODE:RunCycles          11309029                       # Number of cycles decode is running
system.cpu0.decode.DECODE:SquashCycles        1270122                       # Number of cycles decode is squashing
system.cpu0.decode.DECODE:SquashedInsts        100597                       # Number of squashed instructions handled by decode
system.cpu0.decode.DECODE:UnblockCycles        982195                       # Number of cycles decode is unblocking
system.cpu0.dtb.data_accesses                  794086                       # DTB accesses
system.cpu0.dtb.data_acv                          680                       # DTB access violations
system.cpu0.dtb.data_hits                    14244186                       # DTB hits
system.cpu0.dtb.data_misses                     32160                       # DTB misses
system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu0.dtb.fetch_acv                           0                       # ITB acv
system.cpu0.dtb.fetch_hits                          0                       # ITB hits
system.cpu0.dtb.fetch_misses                        0                       # ITB misses
system.cpu0.dtb.read_accesses                  598785                       # DTB read accesses
system.cpu0.dtb.read_acv                          509                       # DTB read access violations
system.cpu0.dtb.read_hits                     8659679                       # DTB read hits
system.cpu0.dtb.read_misses                     26490                       # DTB read misses
system.cpu0.dtb.write_accesses                 195301                       # DTB write accesses
system.cpu0.dtb.write_acv                         171                       # DTB write access violations
system.cpu0.dtb.write_hits                    5584507                       # DTB write hits
system.cpu0.dtb.write_misses                     5670                       # DTB write misses
system.cpu0.fetch.Branches                   12491766                       # Number of branches that fetch encountered
system.cpu0.fetch.CacheLines                  7797156                       # Number of cache lines fetched
system.cpu0.fetch.Cycles                     20279244                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.IcacheSquashes               375144                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.Insts                      63684763                       # Number of instructions fetch has processed
system.cpu0.fetch.MiscStallCycles                 883                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.SquashCycles                 746145                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.branchRate                 0.110732                       # Number of branch fetches per cycle
system.cpu0.fetch.icacheStallCycles           7797156                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.predictedBranches           6757330                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.rate                       0.564528                       # Number of inst fetches per cycle
system.cpu0.fetch.rateDist::samples          79861148                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             0.797444                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.100172                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                67408745     84.41%     84.41% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                  900507      1.13%     85.54% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                 1775612      2.22%     87.76% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                  807193      1.01%     88.77% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                 2749132      3.44%     92.21% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                  585022      0.73%     92.94% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                  680161      0.85%     93.80% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                  829359      1.04%     94.83% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 4125417      5.17%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total            79861148                       # Number of instructions fetched each cycle (Total)
system.cpu0.icache.ReadReq_accesses::0        7797156                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total      7797156                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_avg_miss_latency::0 15068.131136                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12017.324658                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_hits::0            6939758                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total        6939758                       # number of ReadReq hits
system.cpu0.icache.ReadReq_miss_latency   12919385500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_rate::0      0.109963                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_misses::0           857398                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       857398                       # number of ReadReq misses
system.cpu0.icache.ReadReq_mshr_hits            36516                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_miss_latency   9864805500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::0     0.105280                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_misses         820882                       # number of ReadReq MSHR misses
system.cpu0.icache.avg_blocked_cycles::no_mshrs 11596.153846                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu0.icache.avg_refs                  8.455231                       # Average number of references to valid blocks.
system.cpu0.icache.blocked::no_mshrs               52                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_mshrs       603000                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.demand_accesses::0         7797156                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total      7797156                       # number of demand (read+write) accesses
system.cpu0.icache.demand_avg_miss_latency::0 15068.131136                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency 12017.324658                       # average overall mshr miss latency
system.cpu0.icache.demand_hits::0             6939758                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::1                   0                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total         6939758                       # number of demand (read+write) hits
system.cpu0.icache.demand_miss_latency    12919385500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_rate::0       0.109963                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu0.icache.demand_misses::0            857398                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::1                 0                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        857398                       # number of demand (read+write) misses
system.cpu0.icache.demand_mshr_hits             36516                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_miss_latency   9864805500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_rate::0     0.105280                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_misses          820882                       # number of demand (read+write) MSHR misses
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.occ_%::0                  0.995823                       # Average percentage of cache occupancy
system.cpu0.icache.occ_blocks::0           509.861438                       # Average occupied blocks per context
system.cpu0.icache.overall_accesses::0        7797156                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total      7797156                       # number of overall (read+write) accesses
system.cpu0.icache.overall_avg_miss_latency::0 15068.131136                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency 12017.324658                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_hits::0            6939758                       # number of overall hits
system.cpu0.icache.overall_hits::1                  0                       # number of overall hits
system.cpu0.icache.overall_hits::total        6939758                       # number of overall hits
system.cpu0.icache.overall_miss_latency   12919385500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_rate::0      0.109963                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu0.icache.overall_misses::0           857398                       # number of overall misses
system.cpu0.icache.overall_misses::1                0                       # number of overall misses
system.cpu0.icache.overall_misses::total       857398                       # number of overall misses
system.cpu0.icache.overall_mshr_hits            36516                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_miss_latency   9864805500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_rate::0     0.105280                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_misses         820882                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu0.icache.replacements                820254                       # number of replacements
system.cpu0.icache.sampled_refs                820765                       # Sample count of references to valid blocks.
system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu0.icache.tagsinuse               509.861438                       # Cycle average of tags in use
system.cpu0.icache.total_refs                 6939758                       # Total number of references to valid blocks.
system.cpu0.icache.warmup_cycle           24435354000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.writebacks                     108                       # number of writebacks
system.cpu0.idleCycles                       32949400                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.iew.EXEC:branches                 8094203                       # Number of branches executed
system.cpu0.iew.EXEC:nop                      3189422                       # number of nop insts executed
system.cpu0.iew.EXEC:rate                    0.446630                       # Inst execution rate
system.cpu0.iew.EXEC:refs                    14505244                       # number of memory reference insts executed
system.cpu0.iew.EXEC:stores                   5602935                       # Number of stores executed
system.cpu0.iew.EXEC:swp                            0                       # number of swp insts executed
system.cpu0.iew.WB:consumers                 31589475                       # num instructions consuming a value
system.cpu0.iew.WB:count                     50006148                       # cumulative count of insts written-back
system.cpu0.iew.WB:fanout                    0.758030                       # average fanout of values written-back
system.cpu0.iew.WB:penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.WB:penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.iew.WB:producers                 23945765                       # num instructions producing a value
system.cpu0.iew.WB:rate                      0.443275                       # insts written-back per cycle
system.cpu0.iew.WB:sent                      50087986                       # cumulative count of insts sent to commit
system.cpu0.iew.branchMispredicts              712279                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewBlockCycles                9112948                       # Number of cycles IEW is blocking
system.cpu0.iew.iewDispLoadInsts              9340675                       # Number of dispatched load instructions
system.cpu0.iew.iewDispNonSpecInsts           1511795                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewDispSquashedInsts           758903                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispStoreInsts             5843423                       # Number of dispatched store instructions
system.cpu0.iew.iewDispatchedInsts           57183881                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewExecLoadInsts              8902309                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           466602                       # Number of squashed instructions skipped in execute
system.cpu0.iew.iewExecutedInsts             50384547                       # Number of executed instructions
system.cpu0.iew.iewIQFullEvents                 59804                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewLSQFullEvents                 6983                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.iewSquashCycles               1270122                       # Number of cycles IEW is squashing
system.cpu0.iew.iewUnblockCycles               547925                       # Number of cycles IEW is unblocking
system.cpu0.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread.0.cacheBlocked       121839                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.lsq.thread.0.forwLoads         411299                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread.0.ignoredResponses        11485                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread.0.memOrderViolation        38596                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread.0.rescheduledLoads        18609                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread.0.squashedLoads      1250008                       # Number of loads squashed
system.cpu0.iew.lsq.thread.0.squashedStores       418646                       # Number of stores squashed
system.cpu0.iew.memOrderViolationEvents         38596                       # Number of memory order violations
system.cpu0.iew.predictedNotTakenIncorrect       332551                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.predictedTakenIncorrect        379728                       # Number of branches that were predicted taken incorrectly
system.cpu0.ipc                              0.416094                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.416094                       # IPC: Total IPC of All Threads
system.cpu0.iq.ISSUE:FU_type_0::No_OpClass         3763      0.01%      0.01% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::IntAlu       35146664     69.12%     69.12% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::IntMult         56139      0.11%     69.23% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::IntDiv              0      0.00%     69.23% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatAdd        15323      0.03%     69.26% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatCmp            0      0.00%     69.26% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatCvt            0      0.00%     69.26% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     69.26% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatDiv         1880      0.00%     69.27% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     69.27% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::MemRead       9202305     18.10%     87.36% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::MemWrite      5645893     11.10%     98.47% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::IprAccess       779184      1.53%    100.00% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::total        50851151                       # Type of FU issued
system.cpu0.iq.ISSUE:fu_busy_cnt               379787                       # FU busy when requested
system.cpu0.iq.ISSUE:fu_busy_rate            0.007469                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.ISSUE:fu_full::No_OpClass            0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::IntAlu            40748     10.73%     10.73% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::IntMult               0      0.00%     10.73% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::IntDiv                0      0.00%     10.73% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatAdd              0      0.00%     10.73% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatCmp              0      0.00%     10.73% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatCvt              0      0.00%     10.73% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatMult             0      0.00%     10.73% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatDiv              0      0.00%     10.73% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatSqrt             0      0.00%     10.73% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::MemRead          225975     59.50%     70.23% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::MemWrite         113064     29.77%    100.00% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::IprAccess             0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.ISSUE:issued_per_cycle::samples     79861148                       # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::mean     0.636745                       # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::stdev     1.207484                       # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::0     55051799     68.93%     68.93% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::1     12151486     15.22%     84.15% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::2      5444442      6.82%     90.97% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::3      3407774      4.27%     95.23% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::4      2222623      2.78%     98.02% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::5       997342      1.25%     99.27% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::6       433832      0.54%     99.81% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::7       107535      0.13%     99.94% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::8        44315      0.06%    100.00% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::total     79861148                       # Number of insts issued each cycle
system.cpu0.iq.ISSUE:rate                    0.450766                       # Inst issue rate
system.cpu0.iq.iqInstsAdded                  52272510                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqInstsIssued                 50851151                       # Number of instructions issued
system.cpu0.iq.iqNonSpecInstsAdded            1721949                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqSquashedInstsExamined        6732996                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedInstsIssued            24094                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedNonSpecRemoved       1157202                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.iqSquashedOperandsExamined      3425901                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.itb.data_accesses                       0                       # DTB accesses
system.cpu0.itb.data_acv                            0                       # DTB access violations
system.cpu0.itb.data_hits                           0                       # DTB hits
system.cpu0.itb.data_misses                         0                       # DTB misses
system.cpu0.itb.fetch_accesses                 952090                       # ITB accesses
system.cpu0.itb.fetch_acv                         738                       # ITB acv
system.cpu0.itb.fetch_hits                     923140                       # ITB hits
system.cpu0.itb.fetch_misses                    28950                       # ITB misses
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.read_acv                            0                       # DTB read access violations
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.write_acv                           0                       # DTB write access violations
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::wripir                  351      0.22%      0.22% # number of callpals executed
system.cpu0.kern.callpal::wrmces                    1      0.00%      0.22% # number of callpals executed
system.cpu0.kern.callpal::wrfen                     1      0.00%      0.22% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.22% # number of callpals executed
system.cpu0.kern.callpal::swpctx                 3287      2.03%      2.25% # number of callpals executed
system.cpu0.kern.callpal::tbi                      43      0.03%      2.27% # number of callpals executed
system.cpu0.kern.callpal::wrent                     7      0.00%      2.28% # number of callpals executed
system.cpu0.kern.callpal::swpipl               147044     90.75%     93.03% # number of callpals executed
system.cpu0.kern.callpal::rdps                   6369      3.93%     96.96% # number of callpals executed
system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.96% # number of callpals executed
system.cpu0.kern.callpal::wrusp                     3      0.00%     96.96% # number of callpals executed
system.cpu0.kern.callpal::rdusp                     7      0.00%     96.96% # number of callpals executed
system.cpu0.kern.callpal::whami                     2      0.00%     96.96% # number of callpals executed
system.cpu0.kern.callpal::rti                    4450      2.75%     99.71% # number of callpals executed
system.cpu0.kern.callpal::callsys                 330      0.20%     99.91% # number of callpals executed
system.cpu0.kern.callpal::imb                     138      0.09%    100.00% # number of callpals executed
system.cpu0.kern.callpal::total                162036                       # number of callpals executed
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.hwrei                    176105                       # number of hwrei instructions executed
system.cpu0.kern.inst.quiesce                    6623                       # number of quiesce instructions executed
system.cpu0.kern.ipl_count::0                   62137     40.37%     40.37% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21                    238      0.15%     40.53% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22                   1925      1.25%     41.78% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30                    254      0.17%     41.94% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31                  89358     58.06%    100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total              153912                       # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0                    61267     49.13%     49.13% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21                     238      0.19%     49.32% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22                    1925      1.54%     50.87% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30                     254      0.20%     51.07% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31                   61013     48.93%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total               124697                       # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0            1862678817000     97.99%     97.99% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21               96273000      0.01%     98.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22              398546000      0.02%     98.02% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30              103367000      0.01%     98.02% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31            37550788000      1.98%    100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total        1900827791000                       # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0                 0.985999                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31                0.682793                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.mode_good::kernel               1171                      
system.cpu0.kern.mode_good::user                 1172                      
system.cpu0.kern.mode_good::idle                    0                      
system.cpu0.kern.mode_switch::kernel             6890                       # number of protection mode switches
system.cpu0.kern.mode_switch::user               1172                       # number of protection mode switches
system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
system.cpu0.kern.mode_switch_good::kernel     0.169956                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle      no_value                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total     no_value                       # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel      1898857065000     99.90%     99.90% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user          1970718000      0.10%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context                    3288                       # number of times the context was actually changed
system.cpu0.kern.syscall::2                         6      2.99%      2.99% # number of syscalls executed
system.cpu0.kern.syscall::3                        17      8.46%     11.44% # number of syscalls executed
system.cpu0.kern.syscall::4                         3      1.49%     12.94% # number of syscalls executed
system.cpu0.kern.syscall::6                        27     13.43%     26.37% # number of syscalls executed
system.cpu0.kern.syscall::12                        1      0.50%     26.87% # number of syscalls executed
system.cpu0.kern.syscall::17                        9      4.48%     31.34% # number of syscalls executed
system.cpu0.kern.syscall::19                        6      2.99%     34.33% # number of syscalls executed
system.cpu0.kern.syscall::20                        4      1.99%     36.32% # number of syscalls executed
system.cpu0.kern.syscall::23                        1      0.50%     36.82% # number of syscalls executed
system.cpu0.kern.syscall::24                        3      1.49%     38.31% # number of syscalls executed
system.cpu0.kern.syscall::33                        7      3.48%     41.79% # number of syscalls executed
system.cpu0.kern.syscall::41                        2      1.00%     42.79% # number of syscalls executed
system.cpu0.kern.syscall::45                       36     17.91%     60.70% # number of syscalls executed
system.cpu0.kern.syscall::47                        3      1.49%     62.19% # number of syscalls executed
system.cpu0.kern.syscall::48                        7      3.48%     65.67% # number of syscalls executed
system.cpu0.kern.syscall::54                        9      4.48%     70.15% # number of syscalls executed
system.cpu0.kern.syscall::58                        1      0.50%     70.65% # number of syscalls executed
system.cpu0.kern.syscall::59                        5      2.49%     73.13% # number of syscalls executed
system.cpu0.kern.syscall::71                       27     13.43%     86.57% # number of syscalls executed
system.cpu0.kern.syscall::73                        3      1.49%     88.06% # number of syscalls executed
system.cpu0.kern.syscall::74                        7      3.48%     91.54% # number of syscalls executed
system.cpu0.kern.syscall::87                        1      0.50%     92.04% # number of syscalls executed
system.cpu0.kern.syscall::90                        1      0.50%     92.54% # number of syscalls executed
system.cpu0.kern.syscall::92                        7      3.48%     96.02% # number of syscalls executed
system.cpu0.kern.syscall::97                        2      1.00%     97.01% # number of syscalls executed
system.cpu0.kern.syscall::98                        2      1.00%     98.01% # number of syscalls executed
system.cpu0.kern.syscall::132                       1      0.50%     98.51% # number of syscalls executed
system.cpu0.kern.syscall::144                       1      0.50%     99.00% # number of syscalls executed
system.cpu0.kern.syscall::147                       2      1.00%    100.00% # number of syscalls executed
system.cpu0.kern.syscall::total                   201                       # number of syscalls executed
system.cpu0.memDep0.conflictingLoads          2328642                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         1937858                       # Number of conflicting stores.
system.cpu0.memDep0.insertedLoads             9340675                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores            5843423                       # Number of stores inserted to the mem dependence unit.
system.cpu0.numCycles                       112810548                       # number of cpu cycles simulated
system.cpu0.rename.RENAME:BlockCycles        12992019                       # Number of cycles rename is blocking
system.cpu0.rename.RENAME:CommittedMaps      33999562                       # Number of HB maps that are committed
system.cpu0.rename.RENAME:IQFullEvents        1006246                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.RENAME:IdleCycles         33622049                       # Number of cycles rename is idle
system.cpu0.rename.RENAME:LSQFullEvents       1438466                       # Number of times rename has blocked due to LSQ full
system.cpu0.rename.RENAME:ROBFullEvents         43293                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.RENAME:RenameLookups      72562175                       # Number of register rename lookups that rename has made
system.cpu0.rename.RENAME:RenamedInsts       59339637                       # Number of instructions processed by rename
system.cpu0.rename.RENAME:RenamedOperands     39991159                       # Number of destination operands rename has renamed
system.cpu0.rename.RENAME:RunCycles          11032673                       # Number of cycles rename is running
system.cpu0.rename.RENAME:SquashCycles        1270122                       # Number of cycles rename is squashing
system.cpu0.rename.RENAME:UnblockCycles       4054916                       # Number of cycles rename is unblocking
system.cpu0.rename.RENAME:UndoneMaps          5991595                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.RENAME:serializeStallCycles     16889367                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RENAME:serializingInsts      1393634                       # count of serializing insts renamed
system.cpu0.rename.RENAME:skidInsts          10149085                       # count of insts added to the skid buffer
system.cpu0.rename.RENAME:tempSerializingInsts       207632                       # count of temporary serializing insts renamed
system.cpu0.timesIdled                        1187372                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.BPredUnit.BTBHits                 1155732                       # Number of BTB hits
system.cpu1.BPredUnit.BTBLookups              2684041                       # Number of BTB lookups
system.cpu1.BPredUnit.RASInCorrect               8261                       # Number of incorrect RAS predictions.
system.cpu1.BPredUnit.condIncorrect            171129                       # Number of conditional branches incorrect
system.cpu1.BPredUnit.condPredicted           2476500                       # Number of conditional branches predicted
system.cpu1.BPredUnit.lookups                 2988933                       # Number of BP lookups
system.cpu1.BPredUnit.usedRAS                  209112                       # Number of times the RAS was used to get a target.
system.cpu1.commit.COM:branches               1513156                       # Number of branches committed
system.cpu1.commit.COM:bw_lim_events           195927                       # number cycles where commit BW limit reached
system.cpu1.commit.COM:bw_limited                   0                       # number of insts not committed due to BW limits
system.cpu1.commit.COM:committed_per_cycle::samples     17812439                       # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::mean     0.593209                       # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::stdev     1.404519                       # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::0     13432656     75.41%     75.41% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::1      2071277     11.63%     87.04% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::2       798332      4.48%     91.52% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::3       569921      3.20%     94.72% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::4       392752      2.20%     96.93% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::5       150104      0.84%     97.77% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::6       110432      0.62%     98.39% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::7        91038      0.51%     98.90% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::8       195927      1.10%    100.00% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::total     17812439                       # Number of insts commited each cycle
system.cpu1.commit.COM:count                 10566506                       # Number of instructions committed
system.cpu1.commit.COM:loads                  1991573                       # Number of loads committed
system.cpu1.commit.COM:membars                  52753                       # Number of memory barriers committed
system.cpu1.commit.COM:refs                   3374641                       # Number of memory references committed
system.cpu1.commit.COM:swp_count                    0                       # Number of s/w prefetches committed
system.cpu1.commit.branchMispredicts           163273                       # The number of times a branch was mispredicted
system.cpu1.commit.commitCommittedInsts      10566506                       # The number of committed instructions
system.cpu1.commit.commitNonSpecStalls         163051                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.commitSquashedInsts        1705232                       # The number of squashed insts skipped by commit
system.cpu1.committedInsts                   10039690                       # Number of Instructions Simulated
system.cpu1.committedInsts_total             10039690                       # Number of Instructions Simulated
system.cpu1.cpi                              1.952682                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.952682                       # CPI: Total CPI of All Threads
system.cpu1.dcache.LoadLockedReq_accesses::0        46395                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        46395                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11084.323923                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency  8010.474275                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_hits::0        39665                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        39665                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_miss_latency     74597500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_rate::0     0.145059                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_misses::0         6730                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total         6730                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_mshr_hits          763                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency     47798500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0     0.128613                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_misses         5967                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.ReadReq_accesses::0        2059923                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      2059923                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_avg_miss_latency::0 15005.371131                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11669.279162                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_hits::0            1864992                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        1864992                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_miss_latency    2925012000                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_rate::0      0.094630                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_misses::0           194931                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       194931                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_mshr_hits            99875                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_miss_latency   1109235000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::0     0.046145                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_misses          95056                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency     17677500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.StoreCondReq_accesses::0        43203                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        43203                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 13176.417292                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 10174.605229                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_hits::0         39340                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        39340                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_miss_latency     50900500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_rate::0     0.089415                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_misses::0         3863                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total         3863                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_mshr_miss_latency     39304500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0     0.089415                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_misses         3863                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.WriteReq_accesses::0       1333474                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      1333474                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_avg_miss_latency::0 21222.665351                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 18784.142303                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_hits::0           1083830                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       1083830                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_miss_latency   5298111069                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_rate::0     0.187213                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_misses::0          249644                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       249644                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_mshr_hits          201142                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_miss_latency    911068470                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_rate::0     0.036373                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_misses         48502                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency    377673500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.avg_blocked_cycles::no_mshrs  9931.219300                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_refs                 22.846422                       # Average number of references to valid blocks.
system.cpu1.dcache.blocked::no_mshrs             5285                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_mshrs     52486494                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.demand_accesses::0         3393397                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      3393397                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_avg_miss_latency::0 18496.593531                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency 14073.081751                       # average overall mshr miss latency
system.cpu1.dcache.demand_hits::0             2948822                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         2948822                       # number of demand (read+write) hits
system.cpu1.dcache.demand_miss_latency     8223123069                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_rate::0       0.131012                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu1.dcache.demand_misses::0            444575                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        444575                       # number of demand (read+write) misses
system.cpu1.dcache.demand_mshr_hits            301017                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_miss_latency   2020303470                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_rate::0     0.042305                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_misses          143558                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.occ_%::0                  0.932894                       # Average percentage of cache occupancy
system.cpu1.dcache.occ_blocks::0           477.641661                       # Average occupied blocks per context
system.cpu1.dcache.overall_accesses::0        3393397                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      3393397                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_avg_miss_latency::0 18496.593531                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency 14073.081751                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_hits::0            2948822                       # number of overall hits
system.cpu1.dcache.overall_hits::1                  0                       # number of overall hits
system.cpu1.dcache.overall_hits::total        2948822                       # number of overall hits
system.cpu1.dcache.overall_miss_latency    8223123069                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_rate::0      0.131012                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu1.dcache.overall_misses::0           444575                       # number of overall misses
system.cpu1.dcache.overall_misses::1                0                       # number of overall misses
system.cpu1.dcache.overall_misses::total       444575                       # number of overall misses
system.cpu1.dcache.overall_mshr_hits           301017                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_miss_latency   2020303470                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_rate::0     0.042305                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_misses         143558                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_uncacheable_latency    395351000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.replacements                132490                       # number of replacements
system.cpu1.dcache.sampled_refs                132884                       # Sample count of references to valid blocks.
system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu1.dcache.tagsinuse               477.641661                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                 3035924                       # Total number of references to valid blocks.
system.cpu1.dcache.warmup_cycle          1877659074000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.writebacks                   88699                       # number of writebacks
system.cpu1.decode.DECODE:BlockedCycles       6971990                       # Number of cycles decode is blocked
system.cpu1.decode.DECODE:BranchMispred          7938                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DECODE:BranchResolved       127719                       # Number of times decode resolved a branch
system.cpu1.decode.DECODE:DecodedInsts       13891801                       # Number of instructions handled by decode
system.cpu1.decode.DECODE:IdleCycles          8246933                       # Number of cycles decode is idle
system.cpu1.decode.DECODE:RunCycles           2493797                       # Number of cycles decode is running
system.cpu1.decode.DECODE:SquashCycles         302659                       # Number of cycles decode is squashing
system.cpu1.decode.DECODE:SquashedInsts         23688                       # Number of squashed instructions handled by decode
system.cpu1.decode.DECODE:UnblockCycles         99718                       # Number of cycles decode is unblocking
system.cpu1.dtb.data_accesses                  452227                       # DTB accesses
system.cpu1.dtb.data_acv                          183                       # DTB access violations
system.cpu1.dtb.data_hits                     3607185                       # DTB hits
system.cpu1.dtb.data_misses                     12842                       # DTB misses
system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu1.dtb.fetch_acv                           0                       # ITB acv
system.cpu1.dtb.fetch_hits                          0                       # ITB hits
system.cpu1.dtb.fetch_misses                        0                       # ITB misses
system.cpu1.dtb.read_accesses                  320739                       # DTB read accesses
system.cpu1.dtb.read_acv                           82                       # DTB read access violations
system.cpu1.dtb.read_hits                     2181924                       # DTB read hits
system.cpu1.dtb.read_misses                     10502                       # DTB read misses
system.cpu1.dtb.write_accesses                 131488                       # DTB write accesses
system.cpu1.dtb.write_acv                         101                       # DTB write access violations
system.cpu1.dtb.write_hits                    1425261                       # DTB write hits
system.cpu1.dtb.write_misses                     2340                       # DTB write misses
system.cpu1.fetch.Branches                    2988933                       # Number of branches that fetch encountered
system.cpu1.fetch.CacheLines                  1669639                       # Number of cache lines fetched
system.cpu1.fetch.Cycles                      4303594                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.IcacheSquashes               104390                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.Insts                      14140107                       # Number of instructions fetch has processed
system.cpu1.fetch.MiscStallCycles                 288                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.SquashCycles                 190275                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.branchRate                 0.152463                       # Number of branch fetches per cycle
system.cpu1.fetch.icacheStallCycles           1669639                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.predictedBranches           1364844                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.rate                       0.721275                       # Number of inst fetches per cycle
system.cpu1.fetch.rateDist::samples          18115098                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             0.780570                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.128559                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                15489559     85.51%     85.51% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                  208264      1.15%     86.66% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                  323571      1.79%     88.44% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                  199234      1.10%     89.54% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                  375752      2.07%     91.62% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                  125718      0.69%     92.31% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                  169462      0.94%     93.25% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                  249675      1.38%     94.62% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                  973863      5.38%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total            18115098                       # Number of instructions fetched each cycle (Total)
system.cpu1.icache.ReadReq_accesses::0        1669639                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total      1669639                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_avg_miss_latency::0 14675.575285                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11632.875773                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_hits::0            1406074                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total        1406074                       # number of ReadReq hits
system.cpu1.icache.ReadReq_miss_latency    3867968000                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_rate::0      0.157857                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_misses::0           263565                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       263565                       # number of ReadReq misses
system.cpu1.icache.ReadReq_mshr_hits             8225                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_miss_latency   2970338500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::0     0.152931                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_misses         255340                       # number of ReadReq MSHR misses
system.cpu1.icache.avg_blocked_cycles::no_mshrs  5055.555556                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu1.icache.avg_refs                  5.507925                       # Average number of references to valid blocks.
system.cpu1.icache.blocked::no_mshrs                9                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_mshrs        45500                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.demand_accesses::0         1669639                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total      1669639                       # number of demand (read+write) accesses
system.cpu1.icache.demand_avg_miss_latency::0 14675.575285                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency 11632.875773                       # average overall mshr miss latency
system.cpu1.icache.demand_hits::0             1406074                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::1                   0                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total         1406074                       # number of demand (read+write) hits
system.cpu1.icache.demand_miss_latency     3867968000                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_rate::0       0.157857                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu1.icache.demand_misses::0            263565                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::1                 0                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        263565                       # number of demand (read+write) misses
system.cpu1.icache.demand_mshr_hits              8225                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_miss_latency   2970338500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_rate::0     0.152931                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_misses          255340                       # number of demand (read+write) MSHR misses
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.occ_%::0                  0.900435                       # Average percentage of cache occupancy
system.cpu1.icache.occ_blocks::0           461.022508                       # Average occupied blocks per context
system.cpu1.icache.overall_accesses::0        1669639                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total      1669639                       # number of overall (read+write) accesses
system.cpu1.icache.overall_avg_miss_latency::0 14675.575285                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency 11632.875773                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_hits::0            1406074                       # number of overall hits
system.cpu1.icache.overall_hits::1                  0                       # number of overall hits
system.cpu1.icache.overall_hits::total        1406074                       # number of overall hits
system.cpu1.icache.overall_miss_latency    3867968000                       # number of overall miss cycles
system.cpu1.icache.overall_miss_rate::0      0.157857                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu1.icache.overall_misses::0           263565                       # number of overall misses
system.cpu1.icache.overall_misses::1                0                       # number of overall misses
system.cpu1.icache.overall_misses::total       263565                       # number of overall misses
system.cpu1.icache.overall_mshr_hits             8225                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_miss_latency   2970338500                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_rate::0     0.152931                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_misses         255340                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu1.icache.replacements                254770                       # number of replacements
system.cpu1.icache.sampled_refs                255282                       # Sample count of references to valid blocks.
system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu1.icache.tagsinuse               461.022508                       # Cycle average of tags in use
system.cpu1.icache.total_refs                 1406074                       # Total number of references to valid blocks.
system.cpu1.icache.warmup_cycle          1897916485000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.writebacks                      12                       # number of writebacks
system.cpu1.idleCycles                        1489226                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.iew.EXEC:branches                 1621685                       # Number of branches executed
system.cpu1.iew.EXEC:nop                       600518                       # number of nop insts executed
system.cpu1.iew.EXEC:rate                    0.550648                       # Inst execution rate
system.cpu1.iew.EXEC:refs                     3638770                       # number of memory reference insts executed
system.cpu1.iew.EXEC:stores                   1434645                       # Number of stores executed
system.cpu1.iew.EXEC:swp                            0                       # number of swp insts executed
system.cpu1.iew.WB:consumers                  6221893                       # num instructions consuming a value
system.cpu1.iew.WB:count                     10690151                       # cumulative count of insts written-back
system.cpu1.iew.WB:fanout                    0.737580                       # average fanout of values written-back
system.cpu1.iew.WB:penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.WB:penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.iew.WB:producers                  4589145                       # num instructions producing a value
system.cpu1.iew.WB:rate                      0.545296                       # insts written-back per cycle
system.cpu1.iew.WB:sent                      10713297                       # cumulative count of insts sent to commit
system.cpu1.iew.branchMispredicts              177050                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewBlockCycles                 257506                       # Number of cycles IEW is blocking
system.cpu1.iew.iewDispLoadInsts              2306314                       # Number of dispatched load instructions
system.cpu1.iew.iewDispNonSpecInsts            500674                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewDispSquashedInsts           208241                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispStoreInsts             1509678                       # Number of dispatched store instructions
system.cpu1.iew.iewDispatchedInsts           12354884                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewExecLoadInsts              2204125                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts           106415                       # Number of squashed instructions skipped in execute
system.cpu1.iew.iewExecutedInsts             10795075                       # Number of executed instructions
system.cpu1.iew.iewIQFullEvents                  2676                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewLSQFullEvents                 4880                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.iewSquashCycles                302659                       # Number of cycles IEW is squashing
system.cpu1.iew.iewUnblockCycles                10387                       # Number of cycles IEW is unblocking
system.cpu1.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread.0.cacheBlocked        20658                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.lsq.thread.0.forwLoads          67397                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread.0.ignoredResponses         2150                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread.0.memOrderViolation        10614                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread.0.rescheduledLoads          379                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread.0.squashedLoads       314741                       # Number of loads squashed
system.cpu1.iew.lsq.thread.0.squashedStores       126610                       # Number of stores squashed
system.cpu1.iew.memOrderViolationEvents         10614                       # Number of memory order violations
system.cpu1.iew.predictedNotTakenIncorrect       104614                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.predictedTakenIncorrect         72436                       # Number of branches that were predicted taken incorrectly
system.cpu1.ipc                              0.512116                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.512116                       # IPC: Total IPC of All Threads
system.cpu1.iq.ISSUE:FU_type_0::No_OpClass         3525      0.03%      0.03% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::IntAlu        6828006     62.63%     62.67% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::IntMult         17554      0.16%     62.83% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::IntDiv              0      0.00%     62.83% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatAdd        11432      0.10%     62.93% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatCmp            0      0.00%     62.93% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatCvt            0      0.00%     62.93% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     62.93% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatDiv         1762      0.02%     62.95% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     62.95% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::MemRead       2279720     20.91%     83.86% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::MemWrite      1451557     13.32%     97.18% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::IprAccess       307934      2.82%    100.00% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::total        10901490                       # Type of FU issued
system.cpu1.iq.ISSUE:fu_busy_cnt               154119                       # FU busy when requested
system.cpu1.iq.ISSUE:fu_busy_rate            0.014137                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.ISSUE:fu_full::No_OpClass            0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::IntAlu             3997      2.59%      2.59% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::IntMult               0      0.00%      2.59% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::IntDiv                0      0.00%      2.59% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatAdd              0      0.00%      2.59% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatCmp              0      0.00%      2.59% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatCvt              0      0.00%      2.59% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatMult             0      0.00%      2.59% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatDiv              0      0.00%      2.59% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatSqrt             0      0.00%      2.59% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::MemRead           90686     58.84%     61.43% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::MemWrite          59436     38.57%    100.00% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::IprAccess             0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.ISSUE:issued_per_cycle::samples     18115098                       # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::mean     0.601790                       # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::stdev     1.204979                       # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::0     12897978     71.20%     71.20% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::1      2566961     14.17%     85.37% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::2      1067808      5.89%     91.27% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::3       689821      3.81%     95.07% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::4       522358      2.88%     97.96% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::5       233805      1.29%     99.25% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::6        92642      0.51%     99.76% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::7        34659      0.19%     99.95% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::8         9066      0.05%    100.00% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::total     18115098                       # Number of insts issued each cycle
system.cpu1.iq.ISSUE:rate                    0.556076                       # Inst issue rate
system.cpu1.iq.iqInstsAdded                  11198244                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqInstsIssued                 10901490                       # Number of instructions issued
system.cpu1.iq.iqNonSpecInstsAdded             556122                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqSquashedInstsExamined        1641267                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedInstsIssued            10273                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedNonSpecRemoved        393071                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.iqSquashedOperandsExamined       839516                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.itb.data_accesses                       0                       # DTB accesses
system.cpu1.itb.data_acv                            0                       # DTB access violations
system.cpu1.itb.data_hits                           0                       # DTB hits
system.cpu1.itb.data_misses                         0                       # DTB misses
system.cpu1.itb.fetch_accesses                 447863                       # ITB accesses
system.cpu1.itb.fetch_acv                         278                       # ITB acv
system.cpu1.itb.fetch_hits                     439724                       # ITB hits
system.cpu1.itb.fetch_misses                     8139                       # ITB misses
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.read_acv                            0                       # DTB read access violations
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.write_acv                           0                       # DTB write access violations
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu1.kern.callpal::wripir                  254      0.44%      0.45% # number of callpals executed
system.cpu1.kern.callpal::wrmces                    1      0.00%      0.45% # number of callpals executed
system.cpu1.kern.callpal::wrfen                     1      0.00%      0.45% # number of callpals executed
system.cpu1.kern.callpal::swpctx                 1450      2.54%      2.99% # number of callpals executed
system.cpu1.kern.callpal::tbi                      12      0.02%      3.01% # number of callpals executed
system.cpu1.kern.callpal::wrent                     7      0.01%      3.02% # number of callpals executed
system.cpu1.kern.callpal::swpipl                49382     86.51%     89.53% # number of callpals executed
system.cpu1.kern.callpal::rdps                   2383      4.17%     93.71% # number of callpals executed
system.cpu1.kern.callpal::wrkgp                     1      0.00%     93.71% # number of callpals executed
system.cpu1.kern.callpal::wrusp                     4      0.01%     93.71% # number of callpals executed
system.cpu1.kern.callpal::rdusp                     2      0.00%     93.72% # number of callpals executed
system.cpu1.kern.callpal::whami                     3      0.01%     93.72% # number of callpals executed
system.cpu1.kern.callpal::rti                    3352      5.87%     99.60% # number of callpals executed
system.cpu1.kern.callpal::callsys                 187      0.33%     99.92% # number of callpals executed
system.cpu1.kern.callpal::imb                      43      0.08%    100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
system.cpu1.kern.callpal::total                 57084                       # number of callpals executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.hwrei                     64923                       # number of hwrei instructions executed
system.cpu1.kern.inst.quiesce                    2510                       # number of quiesce instructions executed
system.cpu1.kern.ipl_count::0                   20673     37.58%     37.58% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22                   1922      3.49%     41.08% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30                    351      0.64%     41.71% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31                  32062     58.29%    100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total               55008                       # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0                    20166     47.73%     47.73% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22                    1922      4.55%     52.27% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30                     351      0.83%     53.11% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31                   19815     46.89%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total                42254                       # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0            1870782192000     98.44%     98.44% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22              347977500      0.02%     98.46% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30              137627500      0.01%     98.46% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31            29209741000      1.54%    100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total        1900477538000                       # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0                 0.975475                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::31                0.618021                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.mode_good::kernel                849                      
system.cpu1.kern.mode_good::user                  573                      
system.cpu1.kern.mode_good::idle                  276                      
system.cpu1.kern.mode_switch::kernel             1769                       # number of protection mode switches
system.cpu1.kern.mode_switch::user                573                       # number of protection mode switches
system.cpu1.kern.mode_switch::idle               2540                       # number of protection mode switches
system.cpu1.kern.mode_switch_good::kernel     0.479932                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle      0.108661                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total     1.588594                       # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel        6304093000      0.33%      0.33% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user          1020319500      0.05%      0.39% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle        1893140641500     99.61%    100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context                    1451                       # number of times the context was actually changed
system.cpu1.kern.syscall::2                         2      1.60%      1.60% # number of syscalls executed
system.cpu1.kern.syscall::3                        13     10.40%     12.00% # number of syscalls executed
system.cpu1.kern.syscall::4                         1      0.80%     12.80% # number of syscalls executed
system.cpu1.kern.syscall::6                        15     12.00%     24.80% # number of syscalls executed
system.cpu1.kern.syscall::15                        1      0.80%     25.60% # number of syscalls executed
system.cpu1.kern.syscall::17                        6      4.80%     30.40% # number of syscalls executed
system.cpu1.kern.syscall::19                        4      3.20%     33.60% # number of syscalls executed
system.cpu1.kern.syscall::20                        2      1.60%     35.20% # number of syscalls executed
system.cpu1.kern.syscall::23                        3      2.40%     37.60% # number of syscalls executed
system.cpu1.kern.syscall::24                        3      2.40%     40.00% # number of syscalls executed
system.cpu1.kern.syscall::33                        4      3.20%     43.20% # number of syscalls executed
system.cpu1.kern.syscall::45                       18     14.40%     57.60% # number of syscalls executed
system.cpu1.kern.syscall::47                        3      2.40%     60.00% # number of syscalls executed
system.cpu1.kern.syscall::48                        3      2.40%     62.40% # number of syscalls executed
system.cpu1.kern.syscall::54                        1      0.80%     63.20% # number of syscalls executed
system.cpu1.kern.syscall::59                        2      1.60%     64.80% # number of syscalls executed
system.cpu1.kern.syscall::71                       27     21.60%     86.40% # number of syscalls executed
system.cpu1.kern.syscall::74                        9      7.20%     93.60% # number of syscalls executed
system.cpu1.kern.syscall::90                        2      1.60%     95.20% # number of syscalls executed
system.cpu1.kern.syscall::92                        2      1.60%     96.80% # number of syscalls executed
system.cpu1.kern.syscall::132                       3      2.40%     99.20% # number of syscalls executed
system.cpu1.kern.syscall::144                       1      0.80%    100.00% # number of syscalls executed
system.cpu1.kern.syscall::total                   125                       # number of syscalls executed
system.cpu1.memDep0.conflictingLoads           493721                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores          420829                       # Number of conflicting stores.
system.cpu1.memDep0.insertedLoads             2306314                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores            1509678                       # Number of stores inserted to the mem dependence unit.
system.cpu1.numCycles                        19604324                       # number of cpu cycles simulated
system.cpu1.rename.RENAME:BlockCycles          523322                       # Number of cycles rename is blocking
system.cpu1.rename.RENAME:CommittedMaps       7130376                       # Number of HB maps that are committed
system.cpu1.rename.RENAME:IQFullEvents          34965                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.RENAME:IdleCycles          8479727                       # Number of cycles rename is idle
system.cpu1.rename.RENAME:LSQFullEvents        256792                       # Number of times rename has blocked due to LSQ full
system.cpu1.rename.RENAME:ROBFullEvents         15396                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.RENAME:RenameLookups      15372563                       # Number of register rename lookups that rename has made
system.cpu1.rename.RENAME:RenamedInsts       12869198                       # Number of instructions processed by rename
system.cpu1.rename.RENAME:RenamedOperands      8442140                       # Number of destination operands rename has renamed
system.cpu1.rename.RENAME:RunCycles           2348315                       # Number of cycles rename is running
system.cpu1.rename.RENAME:SquashCycles         302659                       # Number of cycles rename is squashing
system.cpu1.rename.RENAME:UnblockCycles        803488                       # Number of cycles rename is unblocking
system.cpu1.rename.RENAME:UndoneMaps          1311764                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.RENAME:serializeStallCycles      5657585                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RENAME:serializingInsts       515686                       # count of serializing insts renamed
system.cpu1.rename.RENAME:skidInsts           2307049                       # count of insts added to the skid buffer
system.cpu1.rename.RENAME:tempSerializingInsts        52733                       # count of temporary serializing insts renamed
system.cpu1.timesIdled                         194546                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.iocache.ReadReq_accesses::1                172                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            172                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::1 115267.430233                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.iocache.ReadReq_avg_mshr_miss_latency 63267.430233                       # average ReadReq mshr miss latency
system.iocache.ReadReq_miss_latency          19825998                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_rate::1                 1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_misses::1                  172                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              172                       # number of ReadReq misses
system.iocache.ReadReq_mshr_miss_latency     10881998                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::1            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_misses                172                       # number of ReadReq MSHR misses
system.iocache.WriteReq_accesses::1             41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_avg_miss_latency::0          inf                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::1 137710.430449                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
system.iocache.WriteReq_avg_mshr_miss_latency 85706.873219                       # average WriteReq mshr miss latency
system.iocache.WriteReq_miss_latency       5722143806                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_rate::1                1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_misses::1               41552                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
system.iocache.WriteReq_mshr_miss_latency   3561291996                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_rate::0          inf                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::1            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_misses             41552                       # number of WriteReq MSHR misses
system.iocache.avg_blocked_cycles::no_mshrs  6177.017118                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.blocked::no_mshrs                10457                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_mshrs      64593068                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
system.iocache.demand_accesses::1               41724                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           41724                       # number of demand (read+write) accesses
system.iocache.demand_avg_miss_latency::0          inf                       # average overall miss latency
system.iocache.demand_avg_miss_latency::1 137617.913048                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.iocache.demand_avg_mshr_miss_latency 85614.370482                       # average overall mshr miss latency
system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
system.iocache.demand_miss_latency         5741969804                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
system.iocache.demand_miss_rate::1                  1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
system.iocache.demand_misses::1                 41724                       # number of demand (read+write) misses
system.iocache.demand_misses::total             41724                       # number of demand (read+write) misses
system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
system.iocache.demand_mshr_miss_latency    3572173994                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_rate::0           inf                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::1             1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_misses               41724                       # number of demand (read+write) MSHR misses
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.iocache.occ_%::1                      0.029205                       # Average percentage of cache occupancy
system.iocache.occ_blocks::1                 0.467285                       # Average occupied blocks per context
system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
system.iocache.overall_accesses::1              41724                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          41724                       # number of overall (read+write) accesses
system.iocache.overall_avg_miss_latency::0          inf                       # average overall miss latency
system.iocache.overall_avg_miss_latency::1 137617.913048                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.iocache.overall_avg_mshr_miss_latency 85614.370482                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.iocache.overall_hits::0                      0                       # number of overall hits
system.iocache.overall_hits::1                      0                       # number of overall hits
system.iocache.overall_hits::total                  0                       # number of overall hits
system.iocache.overall_miss_latency        5741969804                       # number of overall miss cycles
system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
system.iocache.overall_miss_rate::1                 1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
system.iocache.overall_misses::0                    0                       # number of overall misses
system.iocache.overall_misses::1                41724                       # number of overall misses
system.iocache.overall_misses::total            41724                       # number of overall misses
system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
system.iocache.overall_mshr_miss_latency   3572173994                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::1            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_misses              41724                       # number of overall MSHR misses
system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.iocache.replacements                     41692                       # number of replacements
system.iocache.sampled_refs                     41708                       # Sample count of references to valid blocks.
system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
system.iocache.tagsinuse                     0.467285                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.warmup_cycle              1711286407000                       # Cycle when the warmup percentage was hit.
system.iocache.writebacks                       41520                       # number of writebacks
system.l2c.ReadExReq_accesses::0               257280                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::1                42301                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           299581                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_avg_miss_latency::0 55984.106319                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::1 837903.858521                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::2          inf                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency 40324.237567                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_hits::0                   140913                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::1                    34526                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               175439                       # number of ReadExReq hits
system.l2c.ReadExReq_miss_latency          6514702500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_rate::0            0.452297                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::1            0.183802                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_misses::0                 116367                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::1                   7775                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             124142                       # number of ReadExReq misses
system.l2c.ReadExReq_mshr_miss_latency     5005931500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_rate::0       0.482517                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::1       2.934730                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::2            inf                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_misses               124142                       # number of ReadExReq MSHR misses
system.l2c.ReadReq_accesses::0                1807521                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::1                 343124                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2150645                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_avg_miss_latency::0   52801.759863                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::1   3686733.249197                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::2            inf                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.l2c.ReadReq_avg_mshr_miss_latency 40018.781571                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_hits::0                    1503236                       # number of ReadReq hits
system.l2c.ReadReq_hits::1                     338766                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1842002                       # number of ReadReq hits
system.l2c.ReadReq_miss_latency           16066783500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_rate::0              0.168344                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::1              0.012701                       # miss rate for ReadReq accesses
system.l2c.ReadReq_misses::0                   304285                       # number of ReadReq misses
system.l2c.ReadReq_misses::1                     4358                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               308643                       # number of ReadReq misses
system.l2c.ReadReq_mshr_hits                       16                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_miss_latency      12350876500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_rate::0         0.170746                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::1         0.899462                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::2              inf                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_misses                 308627                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_uncacheable_latency    840467500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.SCUpgradeReq_accesses::0               597                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::1               609                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          1206                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_avg_miss_latency::0  4976.234004                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::1  4685.025818                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::2          inf                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total          inf                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40010.195035                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_hits::0                    50                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::1                    28                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                78                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_miss_latency          2722000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_rate::0         0.916248                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::1         0.954023                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_misses::0                 547                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::1                 581                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1128                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_mshr_miss_latency     45131500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_rate::0     1.889447                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::1     1.852217                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::2          inf                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_misses              1128                       # number of SCUpgradeReq MSHR misses
system.l2c.UpgradeReq_accesses::0                2889                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::1                1652                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            4541                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_avg_miss_latency::0  5869.326501                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::1 12325.134512                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::2          inf                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency 40016.488966                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_hits::0                     157                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::1                     351                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 508                       # number of UpgradeReq hits
system.l2c.UpgradeReq_miss_latency           16035000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_rate::0           0.945656                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::1           0.787530                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_misses::0                  2732                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::1                  1301                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              4033                       # number of UpgradeReq misses
system.l2c.UpgradeReq_mshr_miss_latency     161386500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_rate::0      1.395985                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::1      2.441283                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::2           inf                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_misses                4033                       # number of UpgradeReq MSHR misses
system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_mshr_uncacheable_latency   1532909498                       # number of WriteReq MSHR uncacheable cycles
system.l2c.Writeback_accesses::0               810428                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           810428                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_hits::0                   810428                       # number of Writeback hits
system.l2c.Writeback_hits::total               810428                       # number of Writeback hits
system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.l2c.avg_refs                          5.655479                       # Average number of references to valid blocks.
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.demand_accesses::0                 2064801                       # number of demand (read+write) accesses
system.l2c.demand_accesses::1                  385425                       # number of demand (read+write) accesses
system.l2c.demand_accesses::2                       0                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2450226                       # number of demand (read+write) accesses
system.l2c.demand_avg_miss_latency::0    53682.107776                       # average overall miss latency
system.l2c.demand_avg_miss_latency::1    1861162.614358                       # average overall miss latency
system.l2c.demand_avg_miss_latency::2             inf                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.l2c.demand_avg_mshr_miss_latency  40106.403185                       # average overall mshr miss latency
system.l2c.demand_hits::0                     1644149                       # number of demand (read+write) hits
system.l2c.demand_hits::1                      373292                       # number of demand (read+write) hits
system.l2c.demand_hits::2                           0                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2017441                       # number of demand (read+write) hits
system.l2c.demand_miss_latency            22581486000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_rate::0               0.203725                       # miss rate for demand accesses
system.l2c.demand_miss_rate::1               0.031480                       # miss rate for demand accesses
system.l2c.demand_miss_rate::2               no_value                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           no_value                       # miss rate for demand accesses
system.l2c.demand_misses::0                    420652                       # number of demand (read+write) misses
system.l2c.demand_misses::1                     12133                       # number of demand (read+write) misses
system.l2c.demand_misses::2                         0                       # number of demand (read+write) misses
system.l2c.demand_misses::total                432785                       # number of demand (read+write) misses
system.l2c.demand_mshr_hits                        16                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_miss_latency       17356808000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_rate::0          0.209594                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::1          1.122836                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::2               inf                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total           inf                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_misses                  432769                       # number of demand (read+write) MSHR misses
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.l2c.occ_%::0                          0.187903                       # Average percentage of cache occupancy
system.l2c.occ_%::1                          0.005747                       # Average percentage of cache occupancy
system.l2c.occ_%::2                          0.351863                       # Average percentage of cache occupancy
system.l2c.occ_blocks::0                 12314.431078                       # Average occupied blocks per context
system.l2c.occ_blocks::1                   376.630124                       # Average occupied blocks per context
system.l2c.occ_blocks::2                 23059.694781                       # Average occupied blocks per context
system.l2c.overall_accesses::0                2064801                       # number of overall (read+write) accesses
system.l2c.overall_accesses::1                 385425                       # number of overall (read+write) accesses
system.l2c.overall_accesses::2                      0                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2450226                       # number of overall (read+write) accesses
system.l2c.overall_avg_miss_latency::0   53682.107776                       # average overall miss latency
system.l2c.overall_avg_miss_latency::1   1861162.614358                       # average overall miss latency
system.l2c.overall_avg_miss_latency::2            inf                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.l2c.overall_avg_mshr_miss_latency 40106.403185                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.l2c.overall_hits::0                    1644149                       # number of overall hits
system.l2c.overall_hits::1                     373292                       # number of overall hits
system.l2c.overall_hits::2                          0                       # number of overall hits
system.l2c.overall_hits::total                2017441                       # number of overall hits
system.l2c.overall_miss_latency           22581486000                       # number of overall miss cycles
system.l2c.overall_miss_rate::0              0.203725                       # miss rate for overall accesses
system.l2c.overall_miss_rate::1              0.031480                       # miss rate for overall accesses
system.l2c.overall_miss_rate::2              no_value                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          no_value                       # miss rate for overall accesses
system.l2c.overall_misses::0                   420652                       # number of overall misses
system.l2c.overall_misses::1                    12133                       # number of overall misses
system.l2c.overall_misses::2                        0                       # number of overall misses
system.l2c.overall_misses::total               432785                       # number of overall misses
system.l2c.overall_mshr_hits                       16                       # number of overall MSHR hits
system.l2c.overall_mshr_miss_latency      17356808000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_rate::0         0.209594                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::1         1.122836                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::2              inf                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_misses                 432769                       # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_latency   2373376998                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.l2c.replacements                        395546                       # number of replacements
system.l2c.sampled_refs                        431605                       # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
system.l2c.tagsinuse                     35750.755983                       # Cycle average of tags in use
system.l2c.total_refs                         2440933                       # Total number of references to valid blocks.
system.l2c.warmup_cycle                    9270445000                       # Cycle when the warmup percentage was hit.
system.l2c.writebacks                          121345                       # number of writebacks
system.tsunami.ethernet.coalescedRxDesc      no_value                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.coalescedRxIdle      no_value                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.coalescedRxOk        no_value                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.coalescedRxOrn       no_value                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.coalescedSwi         no_value                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.coalescedTotal       no_value                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.coalescedTxDesc      no_value                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.coalescedTxIdle      no_value                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.coalescedTxOk        no_value                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR

---------- End Simulation Statistics   ----------