path: root/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
host_inst_rate                                 149891                       # Simulator instruction rate (inst/s)
host_mem_usage                                 287008                       # Number of bytes of host memory used
host_seconds                                   374.37                       # Real time elapsed on the host
host_tick_rate                             5098345411                       # Simulator tick rate (ticks/s)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                    56115151                       # Number of instructions simulated
sim_seconds                                  1.908681                       # Number of seconds simulated
sim_ticks                                1908681362500                       # Number of ticks simulated
system.cpu0.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.BPredUnit.BTBHits                 6470772                       # Number of BTB hits
system.cpu0.BPredUnit.BTBLookups             12459992                       # Number of BTB lookups
system.cpu0.BPredUnit.RASInCorrect              36652                       # Number of incorrect RAS predictions.
system.cpu0.BPredUnit.condIncorrect            761921                       # Number of conditional branches incorrect
system.cpu0.BPredUnit.condPredicted          11628226                       # Number of conditional branches predicted
system.cpu0.BPredUnit.lookups                13936368                       # Number of BP lookups
system.cpu0.BPredUnit.usedRAS                  988790                       # Number of times the RAS was used to get a target.
system.cpu0.commit.COM:branches               8127927                       # Number of branches committed
system.cpu0.commit.COM:bw_lim_events           948928                       # number cycles where commit BW limit reached
system.cpu0.commit.COM:bw_limited                   0                       # number of insts not committed due to BW limits
system.cpu0.commit.COM:committed_per_cycle::samples     96210525                       # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::mean     0.559994                       # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::stdev     1.324793                       # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::0     73079830     75.96%     75.96% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::1     10159186     10.56%     86.52% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::2      5793964      6.02%     92.54% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::3      2862156      2.97%     95.51% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::4      1992019      2.07%     97.59% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::5       630403      0.66%     98.24% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::6       376031      0.39%     98.63% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::7       368008      0.38%     99.01% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::8       948928      0.99%    100.00% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::total     96210525                       # Number of insts commited each cycle
system.cpu0.commit.COM:count                 53877339                       # Number of instructions committed
system.cpu0.commit.COM:loads                  8834098                       # Number of loads committed
system.cpu0.commit.COM:membars                 219262                       # Number of memory barriers committed
system.cpu0.commit.COM:refs                  14863142                       # Number of memory references committed
system.cpu0.commit.COM:swp_count                    0                       # Number of s/w prefetches committed
system.cpu0.commit.branchMispredicts           723488                       # The number of times a branch was mispredicted
system.cpu0.commit.commitCommittedInsts      53877339                       # The number of committed instructions
system.cpu0.commit.commitNonSpecStalls         642718                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.commitSquashedInsts        8676299                       # The number of squashed insts skipped by commit
system.cpu0.committedInsts                   50753913                       # Number of Instructions Simulated
system.cpu0.committedInsts_total             50753913                       # Number of Instructions Simulated
system.cpu0.cpi                              2.598475                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        2.598475                       # CPI: Total CPI of All Threads
system.cpu0.dcache.LoadLockedReq_accesses::0       205122                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       205122                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 15332.515478                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11584.904538                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_hits::0       183317                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       183317                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_miss_latency    334325500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_rate::0     0.106303                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_misses::0        21805                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        21805                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_mshr_hits         4992                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency    194777000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0     0.081966                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_misses        16813                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.ReadReq_accesses::0        8824783                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      8824783                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_avg_miss_latency::0 24295.121423                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23079.908159                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_hits::0            7389262                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        7389262                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_miss_latency   34876157000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_rate::0      0.162669                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_misses::0          1435521                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      1435521                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_mshr_hits           389370                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_miss_latency  24145069000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::0     0.118547                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_misses        1046151                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency    922902000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.StoreCondReq_accesses::0       210601                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       210601                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 55488.433658                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 52488.433658                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_hits::0        182459                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       182459                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_miss_latency   1561555500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_rate::0     0.133627                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_misses::0        28142                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total        28142                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_mshr_miss_latency   1477129500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0     0.133627                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_misses        28142                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.WriteReq_accesses::0       5803460                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      5803460                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_avg_miss_latency::0 48954.080777                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 54100.546465                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_hits::0           3719396                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       3719396                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_miss_latency 102023437400                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_rate::0     0.359107                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_misses::0         2084064                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      2084064                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_mshr_hits         1707487                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_miss_latency  20373021486                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_rate::0     0.064888                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_misses        376577                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency   1266172497                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.avg_blocked_cycles::no_mshrs  9947.496514                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets        21500                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_refs                  8.716740                       # Average number of references to valid blocks.
system.cpu0.dcache.blocked::no_mshrs           127068                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              7                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_mshrs   1264008487                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets       150500                       # number of cycles access was blocked
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.demand_accesses::0        14628243                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     14628243                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_avg_miss_latency::0 38896.516038                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency 31290.654634                       # average overall mshr miss latency
system.cpu0.dcache.demand_hits::0            11108658                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        11108658                       # number of demand (read+write) hits
system.cpu0.dcache.demand_miss_latency   136899594400                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_rate::0       0.240602                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu0.dcache.demand_misses::0           3519585                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       3519585                       # number of demand (read+write) misses
system.cpu0.dcache.demand_mshr_hits           2096857                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_miss_latency  44518090486                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_rate::0     0.097259                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_misses         1422728                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.occ_%::0                  0.984997                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_%::1                 -0.015306                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_blocks::0           504.318463                       # Average occupied blocks per context
system.cpu0.dcache.occ_blocks::1            -7.836780                       # Average occupied blocks per context
system.cpu0.dcache.overall_accesses::0       14628243                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     14628243                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_avg_miss_latency::0 38896.516038                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency 31290.654634                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_hits::0           11108658                       # number of overall hits
system.cpu0.dcache.overall_hits::1                  0                       # number of overall hits
system.cpu0.dcache.overall_hits::total       11108658                       # number of overall hits
system.cpu0.dcache.overall_miss_latency  136899594400                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_rate::0      0.240602                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu0.dcache.overall_misses::0          3519585                       # number of overall misses
system.cpu0.dcache.overall_misses::1                0                       # number of overall misses
system.cpu0.dcache.overall_misses::total      3519585                       # number of overall misses
system.cpu0.dcache.overall_mshr_hits          2096857                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_miss_latency  44518090486                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_rate::0     0.097259                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_misses        1422728                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_uncacheable_latency   2189074497                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.replacements               1343392                       # number of replacements
system.cpu0.dcache.sampled_refs               1343785                       # Sample count of references to valid blocks.
system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu0.dcache.tagsinuse               500.400077                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                11713425                       # Total number of references to valid blocks.
system.cpu0.dcache.warmup_cycle              21394000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.writebacks                  404610                       # number of writebacks
system.cpu0.decode.DECODE:BlockedCycles      46313195                       # Number of cycles decode is blocked
system.cpu0.decode.DECODE:BranchMispred         39259                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DECODE:BranchResolved       576703                       # Number of times decode resolved a branch
system.cpu0.decode.DECODE:DecodedInsts       69095576                       # Number of instructions handled by decode
system.cpu0.decode.DECODE:IdleCycles         36458125                       # Number of cycles decode is idle
system.cpu0.decode.DECODE:RunCycles          12314815                       # Number of cycles decode is running
system.cpu0.decode.DECODE:SquashCycles        1498947                       # Number of cycles decode is squashing
system.cpu0.decode.DECODE:SquashedInsts        124799                       # Number of squashed instructions handled by decode
system.cpu0.decode.DECODE:UnblockCycles       1124389                       # Number of cycles decode is unblocking
system.cpu0.dtb.data_accesses                  818221                       # DTB accesses
system.cpu0.dtb.data_acv                          799                       # DTB access violations
system.cpu0.dtb.data_hits                    15815368                       # DTB hits
system.cpu0.dtb.data_misses                     34536                       # DTB misses
system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu0.dtb.fetch_acv                           0                       # ITB acv
system.cpu0.dtb.fetch_hits                          0                       # ITB hits
system.cpu0.dtb.fetch_misses                        0                       # ITB misses
system.cpu0.dtb.read_accesses                  609919                       # DTB read accesses
system.cpu0.dtb.read_acv                          595                       # DTB read access violations
system.cpu0.dtb.read_hits                     9601809                       # DTB read hits
system.cpu0.dtb.read_misses                     28742                       # DTB read misses
system.cpu0.dtb.write_accesses                 208302                       # DTB write accesses
system.cpu0.dtb.write_acv                         204                       # DTB write access violations
system.cpu0.dtb.write_hits                    6213559                       # DTB write hits
system.cpu0.dtb.write_misses                     5794                       # DTB write misses
system.cpu0.fetch.Branches                   13936368                       # Number of branches that fetch encountered
system.cpu0.fetch.CacheLines                  8499965                       # Number of cache lines fetched
system.cpu0.fetch.Cycles                     22177505                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.IcacheSquashes               429825                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.Insts                      70536565                       # Number of instructions fetch has processed
system.cpu0.fetch.MiscStallCycles                1947                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.SquashCycles                 890409                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.branchRate                 0.105672                       # Number of branch fetches per cycle
system.cpu0.fetch.icacheStallCycles           8499965                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.predictedBranches           7459562                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.rate                       0.534843                       # Number of inst fetches per cycle
system.cpu0.fetch.rateDist::samples          97709472                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             0.721901                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.017707                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                84062445     86.03%     86.03% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                  970614      0.99%     87.03% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                 1876169      1.92%     88.95% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                  899130      0.92%     89.87% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                 2879231      2.95%     92.81% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                  630716      0.65%     93.46% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                  762992      0.78%     94.24% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                 1157633      1.18%     95.42% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 4470542      4.58%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total            97709472                       # Number of instructions fetched each cycle (Total)
system.cpu0.icache.ReadReq_accesses::0        8499965                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total      8499965                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_avg_miss_latency::0 14903.591508                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11868.979380                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_hits::0            7487466                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total        7487466                       # number of ReadReq hits
system.cpu0.icache.ReadReq_miss_latency   15089871498                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_rate::0      0.119118                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_misses::0          1012499                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      1012499                       # number of ReadReq misses
system.cpu0.icache.ReadReq_mshr_hits            44617                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_miss_latency  11487771500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::0     0.113869                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_misses         967882                       # number of ReadReq MSHR misses
system.cpu0.icache.avg_blocked_cycles::no_mshrs 11795.081967                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu0.icache.avg_refs                  7.736856                       # Average number of references to valid blocks.
system.cpu0.icache.blocked::no_mshrs               61                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_mshrs       719500                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.demand_accesses::0         8499965                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total      8499965                       # number of demand (read+write) accesses
system.cpu0.icache.demand_avg_miss_latency::0 14903.591508                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency 11868.979380                       # average overall mshr miss latency
system.cpu0.icache.demand_hits::0             7487466                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::1                   0                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total         7487466                       # number of demand (read+write) hits
system.cpu0.icache.demand_miss_latency    15089871498                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_rate::0       0.119118                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu0.icache.demand_misses::0           1012499                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::1                 0                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       1012499                       # number of demand (read+write) misses
system.cpu0.icache.demand_mshr_hits             44617                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_miss_latency  11487771500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_rate::0     0.113869                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_misses          967882                       # number of demand (read+write) MSHR misses
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.occ_%::0                  0.995784                       # Average percentage of cache occupancy
system.cpu0.icache.occ_blocks::0           509.841410                       # Average occupied blocks per context
system.cpu0.icache.overall_accesses::0        8499965                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total      8499965                       # number of overall (read+write) accesses
system.cpu0.icache.overall_avg_miss_latency::0 14903.591508                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency 11868.979380                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_hits::0            7487466                       # number of overall hits
system.cpu0.icache.overall_hits::1                  0                       # number of overall hits
system.cpu0.icache.overall_hits::total        7487466                       # number of overall hits
system.cpu0.icache.overall_miss_latency   15089871498                       # number of overall miss cycles
system.cpu0.icache.overall_miss_rate::0      0.119118                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu0.icache.overall_misses::0          1012499                       # number of overall misses
system.cpu0.icache.overall_misses::1                0                       # number of overall misses
system.cpu0.icache.overall_misses::total      1012499                       # number of overall misses
system.cpu0.icache.overall_mshr_hits            44617                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_miss_latency  11487771500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_rate::0     0.113869                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_misses         967882                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu0.icache.replacements                967254                       # number of replacements
system.cpu0.icache.sampled_refs                967766                       # Sample count of references to valid blocks.
system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu0.icache.tagsinuse               509.841410                       # Cycle average of tags in use
system.cpu0.icache.total_refs                 7487466                       # Total number of references to valid blocks.
system.cpu0.icache.warmup_cycle           25290449000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.writebacks                       0                       # number of writebacks
system.cpu0.idleCycles                       34173281                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.iew.EXEC:branches                 8768783                       # Number of branches executed
system.cpu0.iew.EXEC:nop                      3557044                       # number of nop insts executed
system.cpu0.iew.EXEC:rate                    0.415997                       # Inst execution rate
system.cpu0.iew.EXEC:refs                    16085074                       # number of memory reference insts executed
system.cpu0.iew.EXEC:stores                   6233455                       # Number of stores executed
system.cpu0.iew.EXEC:swp                            0                       # number of swp insts executed
system.cpu0.iew.WB:consumers                 32865773                       # num instructions consuming a value
system.cpu0.iew.WB:count                     54347309                       # cumulative count of insts written-back
system.cpu0.iew.WB:fanout                    0.764091                       # average fanout of values written-back
system.cpu0.iew.WB:penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.WB:penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.iew.WB:producers                 25112440                       # num instructions producing a value
system.cpu0.iew.WB:rate                      0.412088                       # insts written-back per cycle
system.cpu0.iew.WB:sent                      54432899                       # cumulative count of insts sent to commit
system.cpu0.iew.branchMispredicts              782239                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewBlockCycles                9442019                       # Number of cycles IEW is blocking
system.cpu0.iew.iewDispLoadInsts             10379600                       # Number of dispatched load instructions
system.cpu0.iew.iewDispNonSpecInsts           1744642                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewDispSquashedInsts           949306                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispStoreInsts             6581023                       # Number of dispatched store instructions
system.cpu0.iew.iewDispatchedInsts           62660146                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewExecLoadInsts              9851619                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           507857                       # Number of squashed instructions skipped in execute
system.cpu0.iew.iewExecutedInsts             54862889                       # Number of executed instructions
system.cpu0.iew.iewIQFullEvents                 45824                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewLSQFullEvents                 5354                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.iewSquashCycles               1498947                       # Number of cycles IEW is squashing
system.cpu0.iew.iewUnblockCycles               539585                       # Number of cycles IEW is unblocking
system.cpu0.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread.0.cacheBlocked       260747                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.lsq.thread.0.forwLoads         417328                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread.0.ignoredResponses        12574                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread.0.memOrderViolation        44391                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread.0.rescheduledLoads        18291                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread.0.squashedLoads      1545502                       # Number of loads squashed
system.cpu0.iew.lsq.thread.0.squashedStores       551979                       # Number of stores squashed
system.cpu0.iew.memOrderViolationEvents         44391                       # Number of memory order violations
system.cpu0.iew.predictedNotTakenIncorrect       381079                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.predictedTakenIncorrect        401160                       # Number of branches that were predicted taken incorrectly
system.cpu0.ipc                              0.384841                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.384841                       # IPC: Total IPC of All Threads
system.cpu0.iq.ISSUE:FU_type_0::No_OpClass         3316      0.01%      0.01% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::IntAlu       37941800     68.52%     68.53% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::IntMult         60296      0.11%     68.64% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::IntDiv              0      0.00%     68.64% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatAdd        15720      0.03%     68.67% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatCmp            0      0.00%     68.67% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatCvt            0      0.00%     68.67% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     68.67% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatDiv         1656      0.00%     68.67% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     68.67% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::MemRead      10184712     18.39%     87.06% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::MemWrite      6276896     11.34%     98.40% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::IprAccess       886350      1.60%    100.00% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::total        55370746                       # Type of FU issued
system.cpu0.iq.ISSUE:fu_busy_cnt               397277                       # FU busy when requested
system.cpu0.iq.ISSUE:fu_busy_rate            0.007175                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.ISSUE:fu_full::No_OpClass            0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::IntAlu            49080     12.35%     12.35% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::IntMult               0      0.00%     12.35% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::IntDiv                0      0.00%     12.35% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatAdd              0      0.00%     12.35% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatCmp              0      0.00%     12.35% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatCvt              0      0.00%     12.35% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatMult             0      0.00%     12.35% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatDiv              0      0.00%     12.35% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatSqrt             0      0.00%     12.35% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::MemRead          256090     64.46%     76.82% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::MemWrite          92107     23.18%    100.00% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::IprAccess             0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.ISSUE:issued_per_cycle::samples     97709472                       # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::mean     0.566688                       # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::stdev     1.134817                       # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::0     70054320     71.70%     71.70% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::1     13865334     14.19%     85.89% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::2      6040088      6.18%     92.07% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::3      3813933      3.90%     95.97% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::4      2397035      2.45%     98.43% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::5       977877      1.00%     99.43% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::6       439666      0.45%     99.88% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::7       101836      0.10%     99.98% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::8        19383      0.02%    100.00% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::total     97709472                       # Number of insts issued each cycle
system.cpu0.iq.ISSUE:rate                    0.419848                       # Inst issue rate
system.cpu0.iq.iqInstsAdded                  57116410                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqInstsIssued                 55370746                       # Number of instructions issued
system.cpu0.iq.iqNonSpecInstsAdded            1986692                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqSquashedInstsExamined        7999373                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedInstsIssued            32356                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedNonSpecRemoved       1343974                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.iqSquashedOperandsExamined      4128104                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.itb.data_accesses                       0                       # DTB accesses
system.cpu0.itb.data_acv                            0                       # DTB access violations
system.cpu0.itb.data_hits                           0                       # DTB hits
system.cpu0.itb.data_misses                         0                       # DTB misses
system.cpu0.itb.fetch_accesses                1054719                       # ITB accesses
system.cpu0.itb.fetch_acv                         886                       # ITB acv
system.cpu0.itb.fetch_hits                    1025087                       # ITB hits
system.cpu0.itb.fetch_misses                    29632                       # ITB misses
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.read_acv                            0                       # DTB read access violations
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.write_acv                           0                       # DTB write access violations
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::wripir                   98      0.05%      0.05% # number of callpals executed
system.cpu0.kern.callpal::wrmces                    1      0.00%      0.05% # number of callpals executed
system.cpu0.kern.callpal::wrfen                     1      0.00%      0.05% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.05% # number of callpals executed
system.cpu0.kern.callpal::swpctx                 3879      2.08%      2.14% # number of callpals executed
system.cpu0.kern.callpal::tbi                      51      0.03%      2.16% # number of callpals executed
system.cpu0.kern.callpal::wrent                     7      0.00%      2.17% # number of callpals executed
system.cpu0.kern.callpal::swpipl               170561     91.53%     93.70% # number of callpals executed
system.cpu0.kern.callpal::rdps                   6398      3.43%     97.13% # number of callpals executed
system.cpu0.kern.callpal::wrkgp                     1      0.00%     97.13% # number of callpals executed
system.cpu0.kern.callpal::wrusp                     3      0.00%     97.13% # number of callpals executed
system.cpu0.kern.callpal::rdusp                     9      0.00%     97.14% # number of callpals executed
system.cpu0.kern.callpal::whami                     2      0.00%     97.14% # number of callpals executed
system.cpu0.kern.callpal::rti                    4815      2.58%     99.72% # number of callpals executed
system.cpu0.kern.callpal::callsys                 381      0.20%     99.93% # number of callpals executed
system.cpu0.kern.callpal::imb                     136      0.07%    100.00% # number of callpals executed
system.cpu0.kern.callpal::total                186345                       # number of callpals executed
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.hwrei                    201175                       # number of hwrei instructions executed
system.cpu0.kern.inst.quiesce                    6392                       # number of quiesce instructions executed
system.cpu0.kern.ipl_count::0                   72147     40.63%     40.63% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21                    239      0.13%     40.77% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22                   1932      1.09%     41.86% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30                      7      0.00%     41.86% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31                 103229     58.14%    100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total              177554                       # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0                    70781     49.24%     49.24% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21                     239      0.17%     49.41% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22                    1932      1.34%     50.75% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30                       7      0.00%     50.76% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31                   70775     49.24%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total               143734                       # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0            1865669134000     97.77%     97.77% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21              102063500      0.01%     97.77% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22              400489500      0.02%     97.79% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30                4470500      0.00%     97.79% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31            42089413000      2.21%    100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total        1908265570500                       # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0                 0.981066                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31                0.685612                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.mode_good::kernel               1283                      
system.cpu0.kern.mode_good::user                 1283                      
system.cpu0.kern.mode_good::idle                    0                      
system.cpu0.kern.mode_switch::kernel             7354                       # number of protection mode switches
system.cpu0.kern.mode_switch::user               1283                       # number of protection mode switches
system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
system.cpu0.kern.mode_switch_good::kernel     0.174463                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle      no_value                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total     no_value                       # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel      1906087309000     99.89%     99.89% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user          2155018500      0.11%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context                    3880                       # number of times the context was actually changed
system.cpu0.kern.syscall::2                         8      3.60%      3.60% # number of syscalls executed
system.cpu0.kern.syscall::3                        19      8.56%     12.16% # number of syscalls executed
system.cpu0.kern.syscall::4                         4      1.80%     13.96% # number of syscalls executed
system.cpu0.kern.syscall::6                        32     14.41%     28.38% # number of syscalls executed
system.cpu0.kern.syscall::12                        1      0.45%     28.83% # number of syscalls executed
system.cpu0.kern.syscall::17                        9      4.05%     32.88% # number of syscalls executed
system.cpu0.kern.syscall::19                       10      4.50%     37.39% # number of syscalls executed
system.cpu0.kern.syscall::20                        6      2.70%     40.09% # number of syscalls executed
system.cpu0.kern.syscall::23                        1      0.45%     40.54% # number of syscalls executed
system.cpu0.kern.syscall::24                        3      1.35%     41.89% # number of syscalls executed
system.cpu0.kern.syscall::33                        7      3.15%     45.05% # number of syscalls executed
system.cpu0.kern.syscall::41                        2      0.90%     45.95% # number of syscalls executed
system.cpu0.kern.syscall::45                       36     16.22%     62.16% # number of syscalls executed
system.cpu0.kern.syscall::47                        3      1.35%     63.51% # number of syscalls executed
system.cpu0.kern.syscall::48                       10      4.50%     68.02% # number of syscalls executed
system.cpu0.kern.syscall::54                       10      4.50%     72.52% # number of syscalls executed
system.cpu0.kern.syscall::58                        1      0.45%     72.97% # number of syscalls executed
system.cpu0.kern.syscall::59                        6      2.70%     75.68% # number of syscalls executed
system.cpu0.kern.syscall::71                       23     10.36%     86.04% # number of syscalls executed
system.cpu0.kern.syscall::73                        3      1.35%     87.39% # number of syscalls executed
system.cpu0.kern.syscall::74                        6      2.70%     90.09% # number of syscalls executed
system.cpu0.kern.syscall::87                        1      0.45%     90.54% # number of syscalls executed
system.cpu0.kern.syscall::90                        3      1.35%     91.89% # number of syscalls executed
system.cpu0.kern.syscall::92                        9      4.05%     95.95% # number of syscalls executed
system.cpu0.kern.syscall::97                        2      0.90%     96.85% # number of syscalls executed
system.cpu0.kern.syscall::98                        2      0.90%     97.75% # number of syscalls executed
system.cpu0.kern.syscall::132                       1      0.45%     98.20% # number of syscalls executed
system.cpu0.kern.syscall::144                       2      0.90%     99.10% # number of syscalls executed
system.cpu0.kern.syscall::147                       2      0.90%    100.00% # number of syscalls executed
system.cpu0.kern.syscall::total                   222                       # number of syscalls executed
system.cpu0.memDep0.conflictingLoads          2868331                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         2616560                       # Number of conflicting stores.
system.cpu0.memDep0.insertedLoads            10379600                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores            6581023                       # Number of stores inserted to the mem dependence unit.
system.cpu0.numCycles                       131882753                       # number of cpu cycles simulated
system.cpu0.rename.RENAME:BlockCycles        13878265                       # Number of cycles rename is blocking
system.cpu0.rename.RENAME:CommittedMaps      36623956                       # Number of HB maps that are committed
system.cpu0.rename.RENAME:IQFullEvents        1040563                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.RENAME:IdleCycles         38000902                       # Number of cycles rename is idle
system.cpu0.rename.RENAME:LSQFullEvents       2220107                       # Number of times rename has blocked due to LSQ full
system.cpu0.rename.RENAME:ROBFullEvents         18213                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.RENAME:RenameLookups      79075810                       # Number of register rename lookups that rename has made
system.cpu0.rename.RENAME:RenamedInsts       65194392                       # Number of instructions processed by rename
system.cpu0.rename.RENAME:RenamedOperands     43691484                       # Number of destination operands rename has renamed
system.cpu0.rename.RENAME:RunCycles          11998481                       # Number of cycles rename is running
system.cpu0.rename.RENAME:SquashCycles        1498947                       # Number of cycles rename is squashing
system.cpu0.rename.RENAME:UnblockCycles       5027996                       # Number of cycles rename is unblocking
system.cpu0.rename.RENAME:UndoneMaps          7067528                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.RENAME:serializeStallCycles     27304879                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RENAME:serializingInsts      1597966                       # count of serializing insts renamed
system.cpu0.rename.RENAME:skidInsts          12274299                       # count of insts added to the skid buffer
system.cpu0.rename.RENAME:tempSerializingInsts       247715                       # count of temporary serializing insts renamed
system.cpu0.timesIdled                        1299056                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.BPredUnit.BTBHits                  641418                       # Number of BTB hits
system.cpu1.BPredUnit.BTBLookups              1453120                       # Number of BTB lookups
system.cpu1.BPredUnit.RASInCorrect               4656                       # Number of incorrect RAS predictions.
system.cpu1.BPredUnit.condIncorrect             99987                       # Number of conditional branches incorrect
system.cpu1.BPredUnit.condPredicted           1369738                       # Number of conditional branches predicted
system.cpu1.BPredUnit.lookups                 1655319                       # Number of BP lookups
system.cpu1.BPredUnit.usedRAS                  114912                       # Number of times the RAS was used to get a target.
system.cpu1.commit.COM:branches                786729                       # Number of branches committed
system.cpu1.commit.COM:bw_lim_events           111651                       # number cycles where commit BW limit reached
system.cpu1.commit.COM:bw_limited                   0                       # number of insts not committed due to BW limits
system.cpu1.commit.COM:committed_per_cycle::samples      9662936                       # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::mean     0.576830                       # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::stdev     1.391062                       # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::0      7270313     75.24%     75.24% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::1      1222307     12.65%     87.89% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::2       443469      4.59%     92.48% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::3       257393      2.66%     95.14% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::4       152904      1.58%     96.72% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::5        87632      0.91%     97.63% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::6        71404      0.74%     98.37% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::7        45863      0.47%     98.84% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::8       111651      1.16%    100.00% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::total      9662936                       # Number of insts commited each cycle
system.cpu1.commit.COM:count                  5573873                       # Number of instructions committed
system.cpu1.commit.COM:loads                  1110708                       # Number of loads committed
system.cpu1.commit.COM:membars                  18999                       # Number of memory barriers committed
system.cpu1.commit.COM:refs                   1809440                       # Number of memory references committed
system.cpu1.commit.COM:swp_count                    0                       # Number of s/w prefetches committed
system.cpu1.commit.branchMispredicts            95993                       # The number of times a branch was mispredicted
system.cpu1.commit.commitCommittedInsts       5573873                       # The number of committed instructions
system.cpu1.commit.commitNonSpecStalls          71139                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.commitSquashedInsts        1244666                       # The number of squashed insts skipped by commit
system.cpu1.committedInsts                    5361238                       # Number of Instructions Simulated
system.cpu1.committedInsts_total              5361238                       # Number of Instructions Simulated
system.cpu1.cpi                              2.006382                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        2.006382                       # CPI: Total CPI of All Threads
system.cpu1.dcache.LoadLockedReq_accesses::0        15265                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        15265                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 14429.127726                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 10666.666667                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_hits::0        13981                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        13981                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_miss_latency     18527000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_rate::0     0.084114                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_misses::0         1284                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total         1284                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_mshr_hits          240                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency     11136000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0     0.068392                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_misses         1044                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.ReadReq_accesses::0        1203979                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      1203979                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_avg_miss_latency::0 18427.853599                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13573.416201                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_hits::0            1110045                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        1110045                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_miss_latency    1731002000                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_rate::0      0.078020                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_misses::0            93934                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total        93934                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_mshr_hits            53146                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_miss_latency    553632500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::0     0.033878                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_misses          40788                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency     15686000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.StoreCondReq_accesses::0        14051                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        14051                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 45874.534161                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 42893.537697                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_hits::0         11636                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        11636                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_miss_latency    110787000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_rate::0     0.171874                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_misses::0         2415                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total         2415                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_mshr_miss_latency    103545000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0     0.171803                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_misses         2414                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.WriteReq_accesses::0        679686                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total       679686                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_avg_miss_latency::0 48846.469056                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 52388.154254                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_hits::0            517989                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total        517989                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_miss_latency   7898327507                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_rate::0     0.237900                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_misses::0          161697                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       161697                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_mshr_hits          135111                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_miss_latency   1392791469                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_rate::0     0.039115                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_misses         26586                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency    309596000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12811.786863                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_refs                 28.408620                       # Average number of references to valid blocks.
system.cpu1.dcache.blocked::no_mshrs            11875                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_mshrs    152139969                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.demand_accesses::0         1883665                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      1883665                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_avg_miss_latency::0 37668.864523                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency 28889.838350                       # average overall mshr miss latency
system.cpu1.dcache.demand_hits::0             1628034                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         1628034                       # number of demand (read+write) hits
system.cpu1.dcache.demand_miss_latency     9629329507                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_rate::0       0.135709                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu1.dcache.demand_misses::0            255631                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        255631                       # number of demand (read+write) misses
system.cpu1.dcache.demand_mshr_hits            188257                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_miss_latency   1946423969                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_rate::0     0.035768                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_misses           67374                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.occ_%::0                  0.773778                       # Average percentage of cache occupancy
system.cpu1.dcache.occ_blocks::0           396.174503                       # Average occupied blocks per context
system.cpu1.dcache.overall_accesses::0        1883665                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      1883665                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_avg_miss_latency::0 37668.864523                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency 28889.838350                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_hits::0            1628034                       # number of overall hits
system.cpu1.dcache.overall_hits::1                  0                       # number of overall hits
system.cpu1.dcache.overall_hits::total        1628034                       # number of overall hits
system.cpu1.dcache.overall_miss_latency    9629329507                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_rate::0      0.135709                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu1.dcache.overall_misses::0           255631                       # number of overall misses
system.cpu1.dcache.overall_misses::1                0                       # number of overall misses
system.cpu1.dcache.overall_misses::total       255631                       # number of overall misses
system.cpu1.dcache.overall_mshr_hits           188257                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_miss_latency   1946423969                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_rate::0     0.035768                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_misses          67374                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_uncacheable_latency    325282000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.replacements                 58281                       # number of replacements
system.cpu1.dcache.sampled_refs                 58793                       # Sample count of references to valid blocks.
system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu1.dcache.tagsinuse               396.174503                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                 1670228                       # Total number of references to valid blocks.
system.cpu1.dcache.warmup_cycle          1884260206000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.writebacks                   26579                       # number of writebacks
system.cpu1.decode.DECODE:BlockedCycles       4231249                       # Number of cycles decode is blocked
system.cpu1.decode.DECODE:BranchMispred          4060                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DECODE:BranchResolved        70345                       # Number of times decode resolved a branch
system.cpu1.decode.DECODE:DecodedInsts        7846841                       # Number of instructions handled by decode
system.cpu1.decode.DECODE:IdleCycles          3945555                       # Number of cycles decode is idle
system.cpu1.decode.DECODE:RunCycles           1457789                       # Number of cycles decode is running
system.cpu1.decode.DECODE:SquashCycles         213951                       # Number of cycles decode is squashing
system.cpu1.decode.DECODE:SquashedInsts         12437                       # Number of squashed instructions handled by decode
system.cpu1.decode.DECODE:UnblockCycles         28342                       # Number of cycles decode is unblocking
system.cpu1.dtb.data_accesses                  436826                       # DTB accesses
system.cpu1.dtb.data_acv                           92                       # DTB access violations
system.cpu1.dtb.data_hits                     2033744                       # DTB hits
system.cpu1.dtb.data_misses                     11106                       # DTB misses
system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu1.dtb.fetch_acv                           0                       # ITB acv
system.cpu1.dtb.fetch_hits                          0                       # ITB hits
system.cpu1.dtb.fetch_misses                        0                       # ITB misses
system.cpu1.dtb.read_accesses                  315884                       # DTB read accesses
system.cpu1.dtb.read_acv                           16                       # DTB read access violations
system.cpu1.dtb.read_hits                     1299460                       # DTB read hits
system.cpu1.dtb.read_misses                      8720                       # DTB read misses
system.cpu1.dtb.write_accesses                 120942                       # DTB write accesses
system.cpu1.dtb.write_acv                          76                       # DTB write access violations
system.cpu1.dtb.write_hits                     734284                       # DTB write hits
system.cpu1.dtb.write_misses                     2386                       # DTB write misses
system.cpu1.fetch.Branches                    1655319                       # Number of branches that fetch encountered
system.cpu1.fetch.CacheLines                   983571                       # Number of cache lines fetched
system.cpu1.fetch.Cycles                      2495244                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.IcacheSquashes                54744                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.Insts                       8005120                       # Number of instructions fetch has processed
system.cpu1.fetch.MiscStallCycles                 124                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.SquashCycles                 119648                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.branchRate                 0.153887                       # Number of branch fetches per cycle
system.cpu1.fetch.icacheStallCycles            983571                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.predictedBranches            756330                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.rate                       0.744199                       # Number of inst fetches per cycle
system.cpu1.fetch.rateDist::samples           9876887                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             0.810490                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.152603                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                 8372049     84.76%     84.76% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                   99748      1.01%     85.77% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                  205638      2.08%     87.86% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                  130058      1.32%     89.17% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                  234183      2.37%     91.54% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                   78658      0.80%     92.34% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                  103423      1.05%     93.39% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                   71678      0.73%     94.11% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                  581452      5.89%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total             9876887                       # Number of instructions fetched each cycle (Total)
system.cpu1.icache.ReadReq_accesses::0         983571                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total       983571                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_avg_miss_latency::0 14895.250407                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11864.081295                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_hits::0             879141                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total         879141                       # number of ReadReq hits
system.cpu1.icache.ReadReq_miss_latency    1555511000                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_rate::0      0.106174                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_misses::0           104430                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       104430                       # number of ReadReq misses
system.cpu1.icache.ReadReq_mshr_hits             4006                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_miss_latency   1191438500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::0     0.102101                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_misses         100424                       # number of ReadReq MSHR misses
system.cpu1.icache.avg_blocked_cycles::no_mshrs  6636.363636                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu1.icache.avg_refs                  8.759351                       # Average number of references to valid blocks.
system.cpu1.icache.blocked::no_mshrs               11                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_mshrs        73000                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.demand_accesses::0          983571                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total       983571                       # number of demand (read+write) accesses
system.cpu1.icache.demand_avg_miss_latency::0 14895.250407                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency 11864.081295                       # average overall mshr miss latency
system.cpu1.icache.demand_hits::0              879141                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::1                   0                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total          879141                       # number of demand (read+write) hits
system.cpu1.icache.demand_miss_latency     1555511000                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_rate::0       0.106174                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu1.icache.demand_misses::0            104430                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::1                 0                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        104430                       # number of demand (read+write) misses
system.cpu1.icache.demand_mshr_hits              4006                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_miss_latency   1191438500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_rate::0     0.102101                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_misses          100424                       # number of demand (read+write) MSHR misses
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.occ_%::0                  0.866895                       # Average percentage of cache occupancy
system.cpu1.icache.occ_blocks::0           443.850090                       # Average occupied blocks per context
system.cpu1.icache.overall_accesses::0         983571                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total       983571                       # number of overall (read+write) accesses
system.cpu1.icache.overall_avg_miss_latency::0 14895.250407                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency 11864.081295                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_hits::0             879141                       # number of overall hits
system.cpu1.icache.overall_hits::1                  0                       # number of overall hits
system.cpu1.icache.overall_hits::total         879141                       # number of overall hits
system.cpu1.icache.overall_miss_latency    1555511000                       # number of overall miss cycles
system.cpu1.icache.overall_miss_rate::0      0.106174                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu1.icache.overall_misses::0           104430                       # number of overall misses
system.cpu1.icache.overall_misses::1                0                       # number of overall misses
system.cpu1.icache.overall_misses::total       104430                       # number of overall misses
system.cpu1.icache.overall_mshr_hits             4006                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_miss_latency   1191438500                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_rate::0     0.102101                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_misses         100424                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu1.icache.replacements                 99855                       # number of replacements
system.cpu1.icache.sampled_refs                100366                       # Sample count of references to valid blocks.
system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu1.icache.tagsinuse               443.850090                       # Cycle average of tags in use
system.cpu1.icache.total_refs                  879141                       # Total number of references to valid blocks.
system.cpu1.icache.warmup_cycle          1897353320500                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.writebacks                       0                       # number of writebacks
system.cpu1.idleCycles                         879803                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.iew.EXEC:branches                  868251                       # Number of branches executed
system.cpu1.iew.EXEC:nop                       253715                       # number of nop insts executed
system.cpu1.iew.EXEC:rate                    0.554813                       # Inst execution rate
system.cpu1.iew.EXEC:refs                     2051713                       # number of memory reference insts executed
system.cpu1.iew.EXEC:stores                    739910                       # Number of stores executed
system.cpu1.iew.EXEC:swp                            0                       # number of swp insts executed
system.cpu1.iew.WB:consumers                  3750224                       # num instructions consuming a value
system.cpu1.iew.WB:count                      5855863                       # cumulative count of insts written-back
system.cpu1.iew.WB:fanout                    0.732329                       # average fanout of values written-back
system.cpu1.iew.WB:penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.WB:penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.iew.WB:producers                  2746396                       # num instructions producing a value
system.cpu1.iew.WB:rate                      0.544393                       # insts written-back per cycle
system.cpu1.iew.WB:sent                       5874071                       # cumulative count of insts sent to commit
system.cpu1.iew.branchMispredicts              104878                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewBlockCycles                 312048                       # Number of cycles IEW is blocking
system.cpu1.iew.iewDispLoadInsts              1391930                       # Number of dispatched load instructions
system.cpu1.iew.iewDispNonSpecInsts            267781                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewDispSquashedInsts           126811                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispStoreInsts              802099                       # Number of dispatched store instructions
system.cpu1.iew.iewDispatchedInsts            6897856                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewExecLoadInsts              1311803                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts            68901                       # Number of squashed instructions skipped in execute
system.cpu1.iew.iewExecutedInsts              5967953                       # Number of executed instructions
system.cpu1.iew.iewIQFullEvents                  3132                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewLSQFullEvents                 1266                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.iewSquashCycles                213951                       # Number of cycles IEW is squashing
system.cpu1.iew.iewUnblockCycles                 8244                       # Number of cycles IEW is unblocking
system.cpu1.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread.0.cacheBlocked        56759                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.lsq.thread.0.forwLoads          34660                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread.0.ignoredResponses         1926                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread.0.memOrderViolation         7014                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread.0.rescheduledLoads          360                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread.0.squashedLoads       281222                       # Number of loads squashed
system.cpu1.iew.lsq.thread.0.squashedStores       103367                       # Number of stores squashed
system.cpu1.iew.memOrderViolationEvents          7014                       # Number of memory order violations
system.cpu1.iew.predictedNotTakenIncorrect        58993                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.predictedTakenIncorrect         45885                       # Number of branches that were predicted taken incorrectly
system.cpu1.ipc                              0.498410                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.498410                       # IPC: Total IPC of All Threads
system.cpu1.iq.ISSUE:FU_type_0::No_OpClass         3973      0.07%      0.07% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::IntAlu        3726705     61.73%     61.80% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::IntMult         10086      0.17%     61.97% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::IntDiv              0      0.00%     61.97% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatAdd        10031      0.17%     62.13% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatCmp            0      0.00%     62.13% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatCvt            0      0.00%     62.13% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     62.13% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatDiv         1986      0.03%     62.16% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     62.16% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::MemRead       1347365     22.32%     84.48% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::MemWrite       752050     12.46%     96.94% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::IprAccess       184660      3.06%    100.00% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::total         6036856                       # Type of FU issued
system.cpu1.iq.ISSUE:fu_busy_cnt               101607                       # FU busy when requested
system.cpu1.iq.ISSUE:fu_busy_rate            0.016831                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.ISSUE:fu_full::No_OpClass            0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::IntAlu             3728      3.67%      3.67% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::IntMult               0      0.00%      3.67% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::IntDiv                0      0.00%      3.67% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatAdd              0      0.00%      3.67% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatCmp              0      0.00%      3.67% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatCvt              0      0.00%      3.67% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatMult             0      0.00%      3.67% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatDiv              0      0.00%      3.67% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatSqrt             0      0.00%      3.67% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::MemRead           63305     62.30%     65.97% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::MemWrite          34574     34.03%    100.00% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::IprAccess             0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.ISSUE:issued_per_cycle::samples      9876887                       # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::mean     0.611210                       # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::stdev     1.231461                       # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::0      7028128     71.16%     71.16% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::1      1406586     14.24%     85.40% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::2       558070      5.65%     91.05% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::3       375734      3.80%     94.85% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::4       282352      2.86%     97.71% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::5       133259      1.35%     99.06% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::6        62266      0.63%     99.69% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::7        26307      0.27%     99.96% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::8         4185      0.04%    100.00% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::total      9876887                       # Number of insts issued each cycle
system.cpu1.iq.ISSUE:rate                    0.561219                       # Inst issue rate
system.cpu1.iq.iqInstsAdded                   6356285                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqInstsIssued                  6036856                       # Number of instructions issued
system.cpu1.iq.iqNonSpecInstsAdded             287856                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqSquashedInstsExamined        1234181                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedInstsIssued             8959                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedNonSpecRemoved        216717                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.iqSquashedOperandsExamined       734853                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.itb.data_accesses                       0                       # DTB accesses
system.cpu1.itb.data_acv                            0                       # DTB access violations
system.cpu1.itb.data_hits                           0                       # DTB hits
system.cpu1.itb.data_misses                         0                       # DTB misses
system.cpu1.itb.fetch_accesses                 347409                       # ITB accesses
system.cpu1.itb.fetch_acv                          92                       # ITB acv
system.cpu1.itb.fetch_hits                     340665                       # ITB hits
system.cpu1.itb.fetch_misses                     6744                       # ITB misses
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.read_acv                            0                       # DTB read access violations
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.write_acv                           0                       # DTB write access violations
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu1.kern.callpal::wripir                    7      0.02%      0.03% # number of callpals executed
system.cpu1.kern.callpal::wrmces                    1      0.00%      0.03% # number of callpals executed
system.cpu1.kern.callpal::wrfen                     1      0.00%      0.03% # number of callpals executed
system.cpu1.kern.callpal::swpctx                  357      1.17%      1.20% # number of callpals executed
system.cpu1.kern.callpal::tbi                       3      0.01%      1.21% # number of callpals executed
system.cpu1.kern.callpal::wrent                     7      0.02%      1.23% # number of callpals executed
system.cpu1.kern.callpal::swpipl                25115     82.21%     83.44% # number of callpals executed
system.cpu1.kern.callpal::rdps                   2369      7.75%     91.20% # number of callpals executed
system.cpu1.kern.callpal::wrkgp                     1      0.00%     91.20% # number of callpals executed
system.cpu1.kern.callpal::wrusp                     4      0.01%     91.21% # number of callpals executed
system.cpu1.kern.callpal::whami                     3      0.01%     91.22% # number of callpals executed
system.cpu1.kern.callpal::rti                    2501      8.19%     99.41% # number of callpals executed
system.cpu1.kern.callpal::callsys                 136      0.45%     99.85% # number of callpals executed
system.cpu1.kern.callpal::imb                      44      0.14%    100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
system.cpu1.kern.callpal::total                 30551                       # number of callpals executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.hwrei                     37164                       # number of hwrei instructions executed
system.cpu1.kern.inst.quiesce                    2263                       # number of quiesce instructions executed
system.cpu1.kern.ipl_count::0                    9735     32.84%     32.84% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22                   1929      6.51%     39.35% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30                     98      0.33%     39.68% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31                  17882     60.32%    100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total               29644                       # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0                     9724     45.49%     45.49% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22                    1929      9.02%     54.51% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30                      98      0.46%     54.97% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31                    9626     45.03%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total                21377                       # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0            1880211308500     98.51%     98.51% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22              349210000      0.02%     98.53% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30               40269500      0.00%     98.53% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31            28079728000      1.47%    100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total        1908680516000                       # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0                 0.998870                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::31                0.538307                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.mode_good::kernel                485                      
system.cpu1.kern.mode_good::user                  463                      
system.cpu1.kern.mode_good::idle                   22                      
system.cpu1.kern.mode_switch::kernel              814                       # number of protection mode switches
system.cpu1.kern.mode_switch::user                463                       # number of protection mode switches
system.cpu1.kern.mode_switch::idle               2046                       # number of protection mode switches
system.cpu1.kern.mode_switch_good::kernel     0.595823                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle      0.010753                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total     1.606576                       # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel        2177635500      0.11%      0.11% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user           994853500      0.05%      0.17% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle        1905508019000     99.83%    100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context                     358                       # number of times the context was actually changed
system.cpu1.kern.syscall::3                        11     10.58%     10.58% # number of syscalls executed
system.cpu1.kern.syscall::6                        10      9.62%     20.19% # number of syscalls executed
system.cpu1.kern.syscall::15                        1      0.96%     21.15% # number of syscalls executed
system.cpu1.kern.syscall::17                        6      5.77%     26.92% # number of syscalls executed
system.cpu1.kern.syscall::23                        3      2.88%     29.81% # number of syscalls executed
system.cpu1.kern.syscall::24                        3      2.88%     32.69% # number of syscalls executed
system.cpu1.kern.syscall::33                        4      3.85%     36.54% # number of syscalls executed
system.cpu1.kern.syscall::45                       18     17.31%     53.85% # number of syscalls executed
system.cpu1.kern.syscall::47                        3      2.88%     56.73% # number of syscalls executed
system.cpu1.kern.syscall::59                        1      0.96%     57.69% # number of syscalls executed
system.cpu1.kern.syscall::71                       31     29.81%     87.50% # number of syscalls executed
system.cpu1.kern.syscall::74                       10      9.62%     97.12% # number of syscalls executed
system.cpu1.kern.syscall::132                       3      2.88%    100.00% # number of syscalls executed
system.cpu1.kern.syscall::total                   104                       # number of syscalls executed
system.cpu1.memDep0.conflictingLoads           249198                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores          232138                       # Number of conflicting stores.
system.cpu1.memDep0.insertedLoads             1391930                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores             802099                       # Number of stores inserted to the mem dependence unit.
system.cpu1.numCycles                        10756690                       # number of cpu cycles simulated
system.cpu1.rename.RENAME:BlockCycles          465609                       # Number of cycles rename is blocking
system.cpu1.rename.RENAME:CommittedMaps       3852724                       # Number of HB maps that are committed
system.cpu1.rename.RENAME:IQFullEvents          44260                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.RENAME:IdleCycles          4077020                       # Number of cycles rename is idle
system.cpu1.rename.RENAME:LSQFullEvents         64277                       # Number of times rename has blocked due to LSQ full
system.cpu1.rename.RENAME:ROBFullEvents            71                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.RENAME:RenameLookups       8954426                       # Number of register rename lookups that rename has made
system.cpu1.rename.RENAME:RenamedInsts        7268297                       # Number of instructions processed by rename
system.cpu1.rename.RENAME:RenamedOperands      4874919                       # Number of destination operands rename has renamed
system.cpu1.rename.RENAME:RunCycles           1341579                       # Number of cycles rename is running
system.cpu1.rename.RENAME:SquashCycles         213951                       # Number of cycles rename is squashing
system.cpu1.rename.RENAME:UnblockCycles        396189                       # Number of cycles rename is unblocking
system.cpu1.rename.RENAME:UndoneMaps          1022193                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.RENAME:serializeStallCycles      3382537                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RENAME:serializingInsts       292831                       # count of serializing insts renamed
system.cpu1.rename.RENAME:skidInsts           1228786                       # count of insts added to the skid buffer
system.cpu1.rename.RENAME:tempSerializingInsts        20447                       # count of temporary serializing insts renamed
system.cpu1.timesIdled                          85032                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.iocache.ReadReq_accesses::1                177                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            177                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::1 115209.028249                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.iocache.ReadReq_avg_mshr_miss_latency 63209.028249                       # average ReadReq mshr miss latency
system.iocache.ReadReq_miss_latency          20391998                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_rate::1                 1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_misses::1                  177                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              177                       # number of ReadReq misses
system.iocache.ReadReq_mshr_miss_latency     11187998                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::1            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_misses                177                       # number of ReadReq MSHR misses
system.iocache.WriteReq_accesses::1             41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_avg_miss_latency::0          inf                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::1 137839.112582                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
system.iocache.WriteReq_avg_mshr_miss_latency 85835.459039                       # average WriteReq mshr miss latency
system.iocache.WriteReq_miss_latency       5727490806                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_rate::1                1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_misses::1               41552                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
system.iocache.WriteReq_mshr_miss_latency   3566634994                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_rate::0          inf                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::1            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_misses             41552                       # number of WriteReq MSHR misses
system.iocache.avg_blocked_cycles::no_mshrs  6168.251363                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.blocked::no_mshrs                10455                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_mshrs      64489068                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
system.iocache.demand_accesses::1               41729                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           41729                       # number of demand (read+write) accesses
system.iocache.demand_avg_miss_latency::0          inf                       # average overall miss latency
system.iocache.demand_avg_miss_latency::1 137743.123583                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.iocache.demand_avg_mshr_miss_latency 85739.485538                       # average overall mshr miss latency
system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
system.iocache.demand_miss_latency         5747882804                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
system.iocache.demand_miss_rate::1                  1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
system.iocache.demand_misses::1                 41729                       # number of demand (read+write) misses
system.iocache.demand_misses::total             41729                       # number of demand (read+write) misses
system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
system.iocache.demand_mshr_miss_latency    3577822992                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_rate::0           inf                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::1             1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_misses               41729                       # number of demand (read+write) MSHR misses
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.iocache.occ_%::1                      0.029808                       # Average percentage of cache occupancy
system.iocache.occ_blocks::1                 0.476933                       # Average occupied blocks per context
system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
system.iocache.overall_accesses::1              41729                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          41729                       # number of overall (read+write) accesses
system.iocache.overall_avg_miss_latency::0          inf                       # average overall miss latency
system.iocache.overall_avg_miss_latency::1 137743.123583                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.iocache.overall_avg_mshr_miss_latency 85739.485538                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.iocache.overall_hits::0                      0                       # number of overall hits
system.iocache.overall_hits::1                      0                       # number of overall hits
system.iocache.overall_hits::total                  0                       # number of overall hits
system.iocache.overall_miss_latency        5747882804                       # number of overall miss cycles
system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
system.iocache.overall_miss_rate::1                 1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
system.iocache.overall_misses::0                    0                       # number of overall misses
system.iocache.overall_misses::1                41729                       # number of overall misses
system.iocache.overall_misses::total            41729                       # number of overall misses
system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
system.iocache.overall_mshr_miss_latency   3577822992                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::1            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_misses              41729                       # number of overall MSHR misses
system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.iocache.replacements                     41697                       # number of replacements
system.iocache.sampled_refs                     41713                       # Sample count of references to valid blocks.
system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
system.iocache.tagsinuse                     0.476933                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.warmup_cycle              1716189422000                       # Cycle when the warmup percentage was hit.
system.iocache.writebacks                       41520                       # number of writebacks
system.l2c.ReadExReq_accesses::0               284402                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::1                21091                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           305493                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_avg_miss_latency::0 56244.064064                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::1 758424.176568                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::2          inf                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency 40208.821305                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_miss_latency         15995924308                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_rate::0                   1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::1                   1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_misses::0                 284402                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::1                  21091                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             305493                       # number of ReadExReq misses
system.l2c.ReadExReq_mshr_miss_latency    12283513447                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_rate::0       1.074159                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::1      14.484519                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::2            inf                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_misses               305493                       # number of ReadExReq MSHR misses
system.l2c.ReadReq_accesses::0                2026908                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::1                 138381                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2165289                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_avg_miss_latency::0   52781.333033                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::1   3774241.528394                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::2            inf                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.l2c.ReadReq_avg_mshr_miss_latency 40018.812855                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_hits::0                    1720929                       # number of ReadReq hits
system.l2c.ReadReq_hits::1                     134102                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1855031                       # number of ReadReq hits
system.l2c.ReadReq_miss_latency           16149979500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_rate::0              0.150959                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::1              0.030922                       # miss rate for ReadReq accesses
system.l2c.ReadReq_misses::0                   305979                       # number of ReadReq misses
system.l2c.ReadReq_misses::1                     4279                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               310258                       # number of ReadReq misses
system.l2c.ReadReq_mshr_hits                       18                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_miss_latency      12415436500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_rate::0         0.153061                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::1         2.241926                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::2              inf                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_misses                 310240                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_uncacheable_latency    840591500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.SCUpgradeReq_accesses::0             27679                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::1              1917                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total         29596                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_avg_miss_latency::0 55685.899057                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::1 804032.342201                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::2          inf                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total          inf                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40005.270983                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_miss_latency       1541330000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_rate::0                1                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::1                1                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_misses::0               27679                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::1                1917                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total           29596                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_mshr_miss_latency   1183996000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_rate::0     1.069258                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::1    15.438706                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::2          inf                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_misses             29596                       # number of SCUpgradeReq MSHR misses
system.l2c.UpgradeReq_accesses::0               95047                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::1                4764                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           99811                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_avg_miss_latency::0 53254.442497                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::1 1062484.256087                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::2          inf                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency 40129.945597                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_miss_latency         5061674996                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_rate::0                  1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::1                  1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_misses::0                 95047                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::1                  4764                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             99811                       # number of UpgradeReq misses
system.l2c.UpgradeReq_mshr_miss_latency    4005410000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_rate::0      1.050123                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::1     20.951092                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::2           inf                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_misses               99811                       # number of UpgradeReq MSHR misses
system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_mshr_uncacheable_latency   1422860998                       # number of WriteReq MSHR uncacheable cycles
system.l2c.Writeback_accesses::0               431189                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           431189                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_hits::0                   431189                       # number of Writeback hits
system.l2c.Writeback_hits::total               431189                       # number of Writeback hits
system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.l2c.avg_refs                          4.720550                       # Average number of references to valid blocks.
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.demand_accesses::0                 2311310                       # number of demand (read+write) accesses
system.l2c.demand_accesses::1                  159472                       # number of demand (read+write) accesses
system.l2c.demand_accesses::2                       0                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2470782                       # number of demand (read+write) accesses
system.l2c.demand_avg_miss_latency::0    54449.421319                       # average overall miss latency
system.l2c.demand_avg_miss_latency::1    1267083.319196                       # average overall miss latency
system.l2c.demand_avg_miss_latency::2             inf                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.l2c.demand_avg_mshr_miss_latency  40113.084644                       # average overall mshr miss latency
system.l2c.demand_hits::0                     1720929                       # number of demand (read+write) hits
system.l2c.demand_hits::1                      134102                       # number of demand (read+write) hits
system.l2c.demand_hits::2                           0                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1855031                       # number of demand (read+write) hits
system.l2c.demand_miss_latency            32145903808                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_rate::0               0.255431                       # miss rate for demand accesses
system.l2c.demand_miss_rate::1               0.159087                       # miss rate for demand accesses
system.l2c.demand_miss_rate::2               no_value                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           no_value                       # miss rate for demand accesses
system.l2c.demand_misses::0                    590381                       # number of demand (read+write) misses
system.l2c.demand_misses::1                     25370                       # number of demand (read+write) misses
system.l2c.demand_misses::2                         0                       # number of demand (read+write) misses
system.l2c.demand_misses::total                615751                       # number of demand (read+write) misses
system.l2c.demand_mshr_hits                        18                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_miss_latency       24698949947                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_rate::0          0.266400                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::1          3.861073                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::2               inf                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total           inf                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_misses                  615733                       # number of demand (read+write) MSHR misses
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.l2c.occ_%::0                          0.092624                       # Average percentage of cache occupancy
system.l2c.occ_%::1                          0.002915                       # Average percentage of cache occupancy
system.l2c.occ_%::2                          0.372149                       # Average percentage of cache occupancy
system.l2c.occ_blocks::0                  6070.232669                       # Average occupied blocks per context
system.l2c.occ_blocks::1                   191.043265                       # Average occupied blocks per context
system.l2c.occ_blocks::2                 24389.134195                       # Average occupied blocks per context
system.l2c.overall_accesses::0                2311310                       # number of overall (read+write) accesses
system.l2c.overall_accesses::1                 159472                       # number of overall (read+write) accesses
system.l2c.overall_accesses::2                      0                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2470782                       # number of overall (read+write) accesses
system.l2c.overall_avg_miss_latency::0   54449.421319                       # average overall miss latency
system.l2c.overall_avg_miss_latency::1   1267083.319196                       # average overall miss latency
system.l2c.overall_avg_miss_latency::2            inf                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.l2c.overall_avg_mshr_miss_latency 40113.084644                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.l2c.overall_hits::0                    1720929                       # number of overall hits
system.l2c.overall_hits::1                     134102                       # number of overall hits
system.l2c.overall_hits::2                          0                       # number of overall hits
system.l2c.overall_hits::total                1855031                       # number of overall hits
system.l2c.overall_miss_latency           32145903808                       # number of overall miss cycles
system.l2c.overall_miss_rate::0              0.255431                       # miss rate for overall accesses
system.l2c.overall_miss_rate::1              0.159087                       # miss rate for overall accesses
system.l2c.overall_miss_rate::2              no_value                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          no_value                       # miss rate for overall accesses
system.l2c.overall_misses::0                   590381                       # number of overall misses
system.l2c.overall_misses::1                    25370                       # number of overall misses
system.l2c.overall_misses::2                        0                       # number of overall misses
system.l2c.overall_misses::total               615751                       # number of overall misses
system.l2c.overall_mshr_hits                       18                       # number of overall MSHR hits
system.l2c.overall_mshr_miss_latency      24698949947                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_rate::0         0.266400                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::1         3.861073                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::2              inf                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_misses                 615733                       # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_latency   2263452498                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.l2c.replacements                        399449                       # number of replacements
system.l2c.sampled_refs                        433881                       # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
system.l2c.tagsinuse                     30650.410129                       # Cycle average of tags in use
system.l2c.total_refs                         2048157                       # Total number of references to valid blocks.
system.l2c.warmup_cycle                    9278771000                       # Cycle when the warmup percentage was hit.
system.l2c.writebacks                          122161                       # number of writebacks
system.tsunami.ethernet.coalescedRxDesc      no_value                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.coalescedRxIdle      no_value                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.coalescedRxOk        no_value                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.coalescedRxOrn       no_value                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.coalescedSwi         no_value                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.coalescedTotal       no_value                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.coalescedTxDesc      no_value                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.coalescedTxIdle      no_value                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.coalescedTxOk        no_value                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR

---------- End Simulation Statistics   ----------