path: root/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect                         0                       # Number of correct BTB predictions (this stat may not work properly.
global.BPredUnit.BTBCorrect                         0                       # Number of correct BTB predictions (this stat may not work properly.
global.BPredUnit.BTBHits                      4976196                       # Number of BTB hits
global.BPredUnit.BTBHits                      2271370                       # Number of BTB hits
global.BPredUnit.BTBLookups                   9270308                       # Number of BTB lookups
global.BPredUnit.BTBLookups                   5052293                       # Number of BTB lookups
global.BPredUnit.RASInCorrect                   24350                       # Number of incorrect RAS predictions.
global.BPredUnit.RASInCorrect                   16405                       # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect                 550496                       # Number of conditional branches incorrect
global.BPredUnit.condIncorrect                 327507                       # Number of conditional branches incorrect
global.BPredUnit.condPredicted                8475186                       # Number of conditional branches predicted
global.BPredUnit.condPredicted                4551940                       # Number of conditional branches predicted
global.BPredUnit.lookups                     10093436                       # Number of BP lookups
global.BPredUnit.lookups                      5538388                       # Number of BP lookups
global.BPredUnit.usedRAS                       690374                       # Number of times the RAS was used to get a target.
global.BPredUnit.usedRAS                       417429                       # Number of times the RAS was used to get a target.
host_inst_rate                                 133092                       # Simulator instruction rate (inst/s)
host_mem_usage                                 294856                       # Number of bytes of host memory used
host_seconds                                   422.19                       # Real time elapsed on the host
host_tick_rate                             4518571306                       # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads            2050532                       # Number of conflicting loads.
memdepunit.memDep.conflictingLoads             906322                       # Number of conflicting loads.
memdepunit.memDep.conflictingStores           1832540                       # Number of conflicting stores.
memdepunit.memDep.conflictingStores            817104                       # Number of conflicting stores.
memdepunit.memDep.insertedLoads               7553751                       # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedLoads               4247428                       # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores              4835994                       # Number of stores inserted to the mem dependence unit.
memdepunit.memDep.insertedStores              2557361                       # Number of stores inserted to the mem dependence unit.
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                    56190549                       # Number of instructions simulated
sim_seconds                                  1.907705                       # Number of seconds simulated
sim_ticks                                1907705384500                       # Number of ticks simulated
system.cpu0.commit.COM:branches               5979895                       # Number of branches committed
system.cpu0.commit.COM:bw_lim_events           670394                       # number cycles where commit BW limit reached
system.cpu0.commit.COM:bw_limited                   0                       # number of insts not committed due to BW limits
system.cpu0.commit.COM:committed_per_cycle.start_dist                     # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle.samples     69432721                      
system.cpu0.commit.COM:committed_per_cycle.min_value            0                      
                               0     52134013   7508.57%           
                               1      7662361   1103.57%           
                               2      4443978    640.04%           
                               3      2023859    291.48%           
                               4      1473823    212.27%           
                               5       453847     65.37%           
                               6       276435     39.81%           
                               7       294011     42.34%           
                               8       670394     96.55%           
system.cpu0.commit.COM:committed_per_cycle.max_value            8                      
system.cpu0.commit.COM:committed_per_cycle.end_dist

system.cpu0.commit.COM:count                 39866260                       # Number of instructions committed
system.cpu0.commit.COM:loads                  6404474                       # Number of loads committed
system.cpu0.commit.COM:membars                 151021                       # Number of memory barriers committed
system.cpu0.commit.COM:refs                  10831640                       # Number of memory references committed
system.cpu0.commit.COM:swp_count                    0                       # Number of s/w prefetches committed
system.cpu0.commit.branchMispredicts           524450                       # The number of times a branch was mispredicted
system.cpu0.commit.commitCommittedInsts      39866260                       # The number of committed instructions
system.cpu0.commit.commitNonSpecStalls         458375                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.commitSquashedInsts        6218747                       # The number of squashed insts skipped by commit
system.cpu0.committedInsts                   37660679                       # Number of Instructions Simulated
system.cpu0.committedInsts_total             37660679                       # Number of Instructions Simulated
system.cpu0.cpi                              2.679241                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        2.679241                       # CPI: Total CPI of All Threads
system.cpu0.dcache.LoadLockedReq_accesses       147686                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_avg_miss_latency 15414.654688                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11879.766663                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_hits          135219                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_miss_latency    192174500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_rate     0.084416                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_misses         12467                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_mshr_hits         3210                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency    109971000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate     0.062680                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_misses         9257                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.ReadReq_accesses           6414696                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_avg_miss_latency 28975.378056                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 28716.351233                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_hits               5468142                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_miss_latency   27426760000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_rate         0.147560                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_misses              946554                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_mshr_hits           250845                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_miss_latency  19978224000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate     0.108455                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_misses         695709                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency    639862500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.StoreCondReq_accesses       156551                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_avg_miss_latency 54667.977283                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 51667.977283                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_hits           140528                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_miss_latency    875945000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_rate     0.102350                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_misses          16023                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_mshr_miss_latency    827876000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_rate     0.102350                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_misses        16023                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.WriteReq_accesses          4258061                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_avg_miss_latency 48857.574152                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 53930.516019                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_hits              2612712                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_miss_latency  80387760774                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_rate        0.386408                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_misses            1645349                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_mshr_hits         1362208                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_miss_latency  15269940236                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_rate     0.066495                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_misses        283141                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency   1050786497                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.avg_blocked_cycles_no_mshrs  9307.072518                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles_no_targets        16250                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_refs                  9.224260                       # Average number of references to valid blocks.
system.cpu0.dcache.blocked_no_mshrs            116343                       # number of cycles access was blocked
system.cpu0.dcache.blocked_no_targets               2                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles_no_mshrs   1082812738                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles_no_targets        32500                       # number of cycles access was blocked
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.demand_accesses           10672757                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_avg_miss_latency 41596.664989                       # average overall miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency 36009.770890                       # average overall mshr miss latency
system.cpu0.dcache.demand_hits                8080854                       # number of demand (read+write) hits
system.cpu0.dcache.demand_miss_latency   107814520774                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_rate          0.242852                       # miss rate for demand accesses
system.cpu0.dcache.demand_misses              2591903                       # number of demand (read+write) misses
system.cpu0.dcache.demand_mshr_hits           1613053                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_miss_latency  35248164236                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_rate     0.091715                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_misses          978850                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.overall_accesses          10672757                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_avg_miss_latency 41596.664989                       # average overall miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency 36009.770890                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_hits               8080854                       # number of overall hits
system.cpu0.dcache.overall_miss_latency  107814520774                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_rate         0.242852                       # miss rate for overall accesses
system.cpu0.dcache.overall_misses             2591903                       # number of overall misses
system.cpu0.dcache.overall_mshr_hits          1613053                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_miss_latency  35248164236                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_rate     0.091715                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_misses         978850                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_uncacheable_latency   1690648997                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.replacements                922726                       # number of replacements
system.cpu0.dcache.sampled_refs                923123                       # Sample count of references to valid blocks.
system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu0.dcache.tagsinuse               442.178159                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                 8515127                       # Total number of references to valid blocks.
system.cpu0.dcache.warmup_cycle              21439000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.writebacks                  297339                       # number of writebacks
system.cpu0.decode.DECODE:BlockedCycles      33638498                       # Number of cycles decode is blocked
system.cpu0.decode.DECODE:BranchMispred         26518                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DECODE:BranchResolved       401379                       # Number of times decode resolved a branch
system.cpu0.decode.DECODE:DecodedInsts       50930127                       # Number of instructions handled by decode
system.cpu0.decode.DECODE:IdleCycles         25726100                       # Number of cycles decode is idle
system.cpu0.decode.DECODE:RunCycles           9143957                       # Number of cycles decode is running
system.cpu0.decode.DECODE:SquashCycles        1094068                       # Number of cycles decode is squashing
system.cpu0.decode.DECODE:SquashedInsts         84180                       # Number of squashed instructions handled by decode
system.cpu0.decode.DECODE:UnblockCycles        924165                       # Number of cycles decode is unblocking
system.cpu0.dtb.accesses                       812672                       # DTB accesses
system.cpu0.dtb.acv                               801                       # DTB access violations
system.cpu0.dtb.hits                         11625470                       # DTB hits
system.cpu0.dtb.misses                          28525                       # DTB misses
system.cpu0.dtb.read_accesses                  605265                       # DTB read accesses
system.cpu0.dtb.read_acv                          596                       # DTB read access violations
system.cpu0.dtb.read_hits                     7063685                       # DTB read hits
system.cpu0.dtb.read_misses                     24056                       # DTB read misses
system.cpu0.dtb.write_accesses                 207407                       # DTB write accesses
system.cpu0.dtb.write_acv                         205                       # DTB write access violations
system.cpu0.dtb.write_hits                    4561785                       # DTB write hits
system.cpu0.dtb.write_misses                     4469                       # DTB write misses
system.cpu0.fetch.Branches                   10093436                       # Number of branches that fetch encountered
system.cpu0.fetch.CacheLines                  6456939                       # Number of cache lines fetched
system.cpu0.fetch.Cycles                     16710993                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.IcacheSquashes               292607                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.Insts                      52006564                       # Number of instructions fetch has processed
system.cpu0.fetch.MiscStallCycles                 345                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.SquashCycles                 660338                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.branchRate                 0.100032                       # Number of branch fetches per cycle
system.cpu0.fetch.icacheStallCycles           6456939                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.predictedBranches           5666570                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.rate                       0.515416                       # Number of inst fetches per cycle
system.cpu0.fetch.rateDist.start_dist                          # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist.samples           70526789                      
system.cpu0.fetch.rateDist.min_value                0                      
                               0     60303520   8550.44%           
                               1       761818    108.02%           
                               2      1433854    203.31%           
                               3       636079     90.19%           
                               4      2329702    330.33%           
                               5       474692     67.31%           
                               6       552513     78.34%           
                               7       815433    115.62%           
                               8      3219178    456.45%           
system.cpu0.fetch.rateDist.max_value                8                      
system.cpu0.fetch.rateDist.end_dist

system.cpu0.icache.ReadReq_accesses           6456939                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_avg_miss_latency 15194.131269                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12131.657762                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_hits               5806696                       # number of ReadReq hits
system.cpu0.icache.ReadReq_miss_latency    9879877499                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_rate         0.100705                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_misses              650243                       # number of ReadReq misses
system.cpu0.icache.ReadReq_mshr_hits            29877                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_miss_latency   7526067999                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate     0.096077                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_misses         620366                       # number of ReadReq MSHR misses
system.cpu0.icache.avg_blocked_cycles_no_mshrs 11808.794118                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu0.icache.avg_refs                  9.361637                       # Average number of references to valid blocks.
system.cpu0.icache.blocked_no_mshrs                34                       # number of cycles access was blocked
system.cpu0.icache.blocked_no_targets               0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles_no_mshrs       401499                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.demand_accesses            6456939                       # number of demand (read+write) accesses
system.cpu0.icache.demand_avg_miss_latency 15194.131269                       # average overall miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency 12131.657762                       # average overall mshr miss latency
system.cpu0.icache.demand_hits                5806696                       # number of demand (read+write) hits
system.cpu0.icache.demand_miss_latency     9879877499                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_rate          0.100705                       # miss rate for demand accesses
system.cpu0.icache.demand_misses               650243                       # number of demand (read+write) misses
system.cpu0.icache.demand_mshr_hits             29877                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_miss_latency   7526067999                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_rate     0.096077                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_misses          620366                       # number of demand (read+write) MSHR misses
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.overall_accesses           6456939                       # number of overall (read+write) accesses
system.cpu0.icache.overall_avg_miss_latency 15194.131269                       # average overall miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency 12131.657762                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_hits               5806696                       # number of overall hits
system.cpu0.icache.overall_miss_latency    9879877499                       # number of overall miss cycles
system.cpu0.icache.overall_miss_rate         0.100705                       # miss rate for overall accesses
system.cpu0.icache.overall_misses              650243                       # number of overall misses
system.cpu0.icache.overall_mshr_hits            29877                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_miss_latency   7526067999                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_rate     0.096077                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_misses         620366                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu0.icache.replacements                619753                       # number of replacements
system.cpu0.icache.sampled_refs                620265                       # Sample count of references to valid blocks.
system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu0.icache.tagsinuse               509.829037                       # Cycle average of tags in use
system.cpu0.icache.total_refs                 5806696                       # Total number of references to valid blocks.
system.cpu0.icache.warmup_cycle           25308080000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.writebacks                       0                       # number of writebacks
system.cpu0.idleCycles                       30375232                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.iew.EXEC:branches                 6436271                       # Number of branches executed
system.cpu0.iew.EXEC:nop                      2512861                       # number of nop insts executed
system.cpu0.iew.EXEC:rate                    0.402649                       # Inst execution rate
system.cpu0.iew.EXEC:refs                    11740634                       # number of memory reference insts executed
system.cpu0.iew.EXEC:stores                   4575971                       # Number of stores executed
system.cpu0.iew.EXEC:swp                            0                       # number of swp insts executed
system.cpu0.iew.WB:consumers                 24161361                       # num instructions consuming a value
system.cpu0.iew.WB:count                     40226140                       # cumulative count of insts written-back
system.cpu0.iew.WB:fanout                    0.779058                       # average fanout of values written-back
system.cpu0.iew.WB:penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.WB:penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.iew.WB:producers                 18823101                       # num instructions producing a value
system.cpu0.iew.WB:rate                      0.398665                       # insts written-back per cycle
system.cpu0.iew.WB:sent                      40293974                       # cumulative count of insts sent to commit
system.cpu0.iew.branchMispredicts              568843                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewBlockCycles                7178022                       # Number of cycles IEW is blocking
system.cpu0.iew.iewDispLoadInsts              7553751                       # Number of dispatched load instructions
system.cpu0.iew.iewDispNonSpecInsts           1229599                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewDispSquashedInsts           771955                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispStoreInsts             4835994                       # Number of dispatched store instructions
system.cpu0.iew.iewDispatchedInsts           46191067                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewExecLoadInsts              7164663                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           359395                       # Number of squashed instructions skipped in execute
system.cpu0.iew.iewExecutedInsts             40628051                       # Number of executed instructions
system.cpu0.iew.iewIQFullEvents                 33755                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewLSQFullEvents                 4184                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.iewSquashCycles               1094068                       # Number of cycles IEW is squashing
system.cpu0.iew.iewUnblockCycles               453365                       # Number of cycles IEW is unblocking
system.cpu0.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread.0.cacheBlocked       243041                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.lsq.thread.0.forwLoads         357779                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread.0.ignoredResponses         8886                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread.0.memOrderViolation        34084                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread.0.rescheduledLoads        12238                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread.0.squashedLoads      1149277                       # Number of loads squashed
system.cpu0.iew.lsq.thread.0.squashedStores       408828                       # Number of stores squashed
system.cpu0.iew.memOrderViolationEvents         34084                       # Number of memory order violations
system.cpu0.iew.predictedNotTakenIncorrect       255799                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.predictedTakenIncorrect        313044                       # Number of branches that were predicted taken incorrectly
system.cpu0.ipc                              0.373240                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.373240                       # IPC: Total IPC of All Threads
system.cpu0.iq.ISSUE:FU_type_0               40987446                       # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0.start_dist
                      No_OpClass         3326      0.01%            # Type of FU issued
                          IntAlu     28267902     68.97%            # Type of FU issued
                         IntMult        42211      0.10%            # Type of FU issued
                          IntDiv            0      0.00%            # Type of FU issued
                        FloatAdd        12076      0.03%            # Type of FU issued
                        FloatCmp            0      0.00%            # Type of FU issued
                        FloatCvt            0      0.00%            # Type of FU issued
                       FloatMult            0      0.00%            # Type of FU issued
                        FloatDiv         1657      0.00%            # Type of FU issued
                       FloatSqrt            0      0.00%            # Type of FU issued
                         MemRead      7398183     18.05%            # Type of FU issued
                        MemWrite      4612040     11.25%            # Type of FU issued
                       IprAccess       650051      1.59%            # Type of FU issued
                    InstPrefetch            0      0.00%            # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0.end_dist
system.cpu0.iq.ISSUE:fu_busy_cnt               290461                       # FU busy when requested
system.cpu0.iq.ISSUE:fu_busy_rate            0.007087                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.ISSUE:fu_full.start_dist
                      No_OpClass            0      0.00%            # attempts to use FU when none available
                          IntAlu        33502     11.53%            # attempts to use FU when none available
                         IntMult            0      0.00%            # attempts to use FU when none available
                          IntDiv            0      0.00%            # attempts to use FU when none available
                        FloatAdd            0      0.00%            # attempts to use FU when none available
                        FloatCmp            0      0.00%            # attempts to use FU when none available
                        FloatCvt            0      0.00%            # attempts to use FU when none available
                       FloatMult            0      0.00%            # attempts to use FU when none available
                        FloatDiv            0      0.00%            # attempts to use FU when none available
                       FloatSqrt            0      0.00%            # attempts to use FU when none available
                         MemRead       185625     63.91%            # attempts to use FU when none available
                        MemWrite        71334     24.56%            # attempts to use FU when none available
                       IprAccess            0      0.00%            # attempts to use FU when none available
                    InstPrefetch            0      0.00%            # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full.end_dist
system.cpu0.iq.ISSUE:issued_per_cycle.start_dist                     # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle.samples     70526789                      
system.cpu0.iq.ISSUE:issued_per_cycle.min_value            0                      
                               0     49764698   7056.14%           
                               1     10507711   1489.89%           
                               2      4625293    655.82%           
                               3      2839060    402.55%           
                               4      1729945    245.29%           
                               5       663621     94.09%           
                               6       315226     44.70%           
                               7        67152      9.52%           
                               8        14083      2.00%           
system.cpu0.iq.ISSUE:issued_per_cycle.max_value            8                      
system.cpu0.iq.ISSUE:issued_per_cycle.end_dist

system.cpu0.iq.ISSUE:rate                    0.406210                       # Inst issue rate
system.cpu0.iq.iqInstsAdded                  42280485                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqInstsIssued                 40987446                       # Number of instructions issued
system.cpu0.iq.iqNonSpecInstsAdded            1397721                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqSquashedInstsExamined        5737873                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedInstsIssued            23379                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedNonSpecRemoved        939346                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.iqSquashedOperandsExamined      3058467                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.itb.accesses                       875811                       # ITB accesses
system.cpu0.itb.acv                               900                       # ITB acv
system.cpu0.itb.hits                           845925                       # ITB hits
system.cpu0.itb.misses                          29886                       # ITB misses
system.cpu0.kern.callpal                       129578                       # number of callpals executed
system.cpu0.kern.callpal_cserve                     1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal_wripir                    96      0.07%      0.07% # number of callpals executed
system.cpu0.kern.callpal_wrmces                     1      0.00%      0.08% # number of callpals executed
system.cpu0.kern.callpal_wrfen                      1      0.00%      0.08% # number of callpals executed
system.cpu0.kern.callpal_wrvptptr                   1      0.00%      0.08% # number of callpals executed
system.cpu0.kern.callpal_swpctx                  2410      1.86%      1.94% # number of callpals executed
system.cpu0.kern.callpal_tbi                       51      0.04%      1.98% # number of callpals executed
system.cpu0.kern.callpal_wrent                      7      0.01%      1.98% # number of callpals executed
system.cpu0.kern.callpal_swpipl                116005     89.53%     91.51% # number of callpals executed
system.cpu0.kern.callpal_rdps                    6357      4.91%     96.41% # number of callpals executed
system.cpu0.kern.callpal_wrkgp                      1      0.00%     96.41% # number of callpals executed
system.cpu0.kern.callpal_wrusp                      3      0.00%     96.42% # number of callpals executed
system.cpu0.kern.callpal_rdusp                      9      0.01%     96.42% # number of callpals executed
system.cpu0.kern.callpal_whami                      2      0.00%     96.42% # number of callpals executed
system.cpu0.kern.callpal_rti                     4116      3.18%     99.60% # number of callpals executed
system.cpu0.kern.callpal_callsys                  381      0.29%     99.90% # number of callpals executed
system.cpu0.kern.callpal_imb                      136      0.10%    100.00% # number of callpals executed
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.hwrei                    144417                       # number of hwrei instructions executed
system.cpu0.kern.inst.quiesce                    4856                       # number of quiesce instructions executed
system.cpu0.kern.ipl_count                     122308                       # number of times we switched to this ipl
system.cpu0.kern.ipl_count_0                    47763     39.05%     39.05% # number of times we switched to this ipl
system.cpu0.kern.ipl_count_21                     239      0.20%     39.25% # number of times we switched to this ipl
system.cpu0.kern.ipl_count_22                    1931      1.58%     40.83% # number of times we switched to this ipl
system.cpu0.kern.ipl_count_30                      17      0.01%     40.84% # number of times we switched to this ipl
system.cpu0.kern.ipl_count_31                   72358     59.16%    100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_good                       96397                       # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good_0                     47113     48.87%     48.87% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good_21                      239      0.25%     49.12% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good_22                     1931      2.00%     51.13% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good_30                       17      0.02%     51.14% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good_31                    47097     48.86%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks               1907288793500                       # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks_0             1871606924500     98.13%     98.13% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks_21               101495000      0.01%     98.13% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks_22               397995000      0.02%     98.16% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks_30                 9331000      0.00%     98.16% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks_31             35173048000      1.84%    100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used_0                  0.986391                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used_21                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used_22                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used_30                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used_31                 0.650889                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.mode_good_kernel                1283                      
system.cpu0.kern.mode_good_user                  1283                      
system.cpu0.kern.mode_good_idle                     0                      
system.cpu0.kern.mode_switch_kernel              5894                       # number of protection mode switches
system.cpu0.kern.mode_switch_user                1283                       # number of protection mode switches
system.cpu0.kern.mode_switch_idle                   0                       # number of protection mode switches
system.cpu0.kern.mode_switch_good        <err: div-0>                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good_kernel     0.217679                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good_user              1                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good_idle   <err: div-0>                       # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks_kernel       1905143965500     99.89%     99.89% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks_user           2121516000      0.11%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks_idle                    0      0.00%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context                    2411                       # number of times the context was actually changed
system.cpu0.kern.syscall                          222                       # number of syscalls executed
system.cpu0.kern.syscall_2                          8      3.60%      3.60% # number of syscalls executed
system.cpu0.kern.syscall_3                         19      8.56%     12.16% # number of syscalls executed
system.cpu0.kern.syscall_4                          4      1.80%     13.96% # number of syscalls executed
system.cpu0.kern.syscall_6                         32     14.41%     28.38% # number of syscalls executed
system.cpu0.kern.syscall_12                         1      0.45%     28.83% # number of syscalls executed
system.cpu0.kern.syscall_17                         9      4.05%     32.88% # number of syscalls executed
system.cpu0.kern.syscall_19                        10      4.50%     37.39% # number of syscalls executed
system.cpu0.kern.syscall_20                         6      2.70%     40.09% # number of syscalls executed
system.cpu0.kern.syscall_23                         1      0.45%     40.54% # number of syscalls executed
system.cpu0.kern.syscall_24                         3      1.35%     41.89% # number of syscalls executed
system.cpu0.kern.syscall_33                         7      3.15%     45.05% # number of syscalls executed
system.cpu0.kern.syscall_41                         2      0.90%     45.95% # number of syscalls executed
system.cpu0.kern.syscall_45                        36     16.22%     62.16% # number of syscalls executed
system.cpu0.kern.syscall_47                         3      1.35%     63.51% # number of syscalls executed
system.cpu0.kern.syscall_48                        10      4.50%     68.02% # number of syscalls executed
system.cpu0.kern.syscall_54                        10      4.50%     72.52% # number of syscalls executed
system.cpu0.kern.syscall_58                         1      0.45%     72.97% # number of syscalls executed
system.cpu0.kern.syscall_59                         6      2.70%     75.68% # number of syscalls executed
system.cpu0.kern.syscall_71                        23     10.36%     86.04% # number of syscalls executed
system.cpu0.kern.syscall_73                         3      1.35%     87.39% # number of syscalls executed
system.cpu0.kern.syscall_74                         6      2.70%     90.09% # number of syscalls executed
system.cpu0.kern.syscall_87                         1      0.45%     90.54% # number of syscalls executed
system.cpu0.kern.syscall_90                         3      1.35%     91.89% # number of syscalls executed
system.cpu0.kern.syscall_92                         9      4.05%     95.95% # number of syscalls executed
system.cpu0.kern.syscall_97                         2      0.90%     96.85% # number of syscalls executed
system.cpu0.kern.syscall_98                         2      0.90%     97.75% # number of syscalls executed
system.cpu0.kern.syscall_132                        1      0.45%     98.20% # number of syscalls executed
system.cpu0.kern.syscall_144                        2      0.90%     99.10% # number of syscalls executed
system.cpu0.kern.syscall_147                        2      0.90%    100.00% # number of syscalls executed
system.cpu0.numCycles                       100902021                       # number of cpu cycles simulated
system.cpu0.rename.RENAME:BlockCycles        10627682                       # Number of cycles rename is blocking
system.cpu0.rename.RENAME:CommittedMaps      27337911                       # Number of HB maps that are committed
system.cpu0.rename.RENAME:IQFullEvents         742849                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.RENAME:IdleCycles         26930411                       # Number of cycles rename is idle
system.cpu0.rename.RENAME:LSQFullEvents       1646609                       # Number of times rename has blocked due to LSQ full
system.cpu0.rename.RENAME:ROBFullEvents         16617                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.RENAME:RenameLookups      58880309                       # Number of register rename lookups that rename has made
system.cpu0.rename.RENAME:RenamedInsts       48158423                       # Number of instructions processed by rename
system.cpu0.rename.RENAME:RenamedOperands     32535865                       # Number of destination operands rename has renamed
system.cpu0.rename.RENAME:RunCycles           9104795                       # Number of cycles rename is running
system.cpu0.rename.RENAME:SquashCycles        1094068                       # Number of cycles rename is squashing
system.cpu0.rename.RENAME:UnblockCycles       3612727                       # Number of cycles rename is unblocking
system.cpu0.rename.RENAME:UndoneMaps          5197954                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.RENAME:serializeStallCycles     19157104                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RENAME:serializingInsts      1163461                       # count of serializing insts renamed
system.cpu0.rename.RENAME:skidInsts           8536821                       # count of insts added to the skid buffer
system.cpu0.rename.RENAME:tempSerializingInsts       181475                       # count of temporary serializing insts renamed
system.cpu0.timesIdled                         904725                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.commit.COM:branches               2947825                       # Number of branches committed
system.cpu1.commit.COM:bw_lim_events           401526                       # number cycles where commit BW limit reached
system.cpu1.commit.COM:bw_limited                   0                       # number of insts not committed due to BW limits
system.cpu1.commit.COM:committed_per_cycle.start_dist                     # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle.samples     37477455                      
system.cpu1.commit.COM:committed_per_cycle.min_value            0                      
                               0     29419466   7849.91%           
                               1      3577484    954.57%           
                               2      1728132    461.11%           
                               3      1049888    280.14%           
                               4       708571    189.07%           
                               5       265965     70.97%           
                               6       180885     48.27%           
                               7       145538     38.83%           
                               8       401526    107.14%           
system.cpu1.commit.COM:committed_per_cycle.max_value            8                      
system.cpu1.commit.COM:committed_per_cycle.end_dist

system.cpu1.commit.COM:count                 19663805                       # Number of instructions committed
system.cpu1.commit.COM:loads                  3551077                       # Number of loads committed
system.cpu1.commit.COM:membars                  87378                       # Number of memory barriers committed
system.cpu1.commit.COM:refs                   5861573                       # Number of memory references committed
system.cpu1.commit.COM:swp_count                    0                       # Number of s/w prefetches committed
system.cpu1.commit.branchMispredicts           311117                       # The number of times a branch was mispredicted
system.cpu1.commit.commitCommittedInsts      19663805                       # The number of committed instructions
system.cpu1.commit.commitNonSpecStalls         255745                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.commitSquashedInsts        3736987                       # The number of squashed insts skipped by commit
system.cpu1.committedInsts                   18529870                       # Number of Instructions Simulated
system.cpu1.committedInsts_total             18529870                       # Number of Instructions Simulated
system.cpu1.cpi                              2.312190                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        2.312190                       # CPI: Total CPI of All Threads
system.cpu1.dcache.LoadLockedReq_accesses        72126                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_avg_miss_latency 14445.783133                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 11202.181535                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_hits           59842                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_miss_latency    177452000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_rate     0.170313                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_misses         12284                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_mshr_hits         2016                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency    115024000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate     0.142362                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_misses        10268                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.ReadReq_accesses           3589521                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_avg_miss_latency 15546.334532                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11998.783257                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_hits               2947311                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_miss_latency    9984011500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_rate         0.178912                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_misses              642210                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_mshr_hits           211141                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_miss_latency   5172303500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate     0.120091                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_misses         431069                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency    298579500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.StoreCondReq_accesses        68169                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_avg_miss_latency 54676.100066                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 51676.100066                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_hits            51420                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_miss_latency    915770000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_rate     0.245698                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_misses          16749                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_mshr_miss_latency    865523000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_rate     0.245698                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_misses        16749                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.WriteReq_accesses          2234886                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_avg_miss_latency 49366.448141                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 54247.795546                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_hits              1540754                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_miss_latency  34266831381                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_rate        0.310589                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_misses             694132                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_mshr_hits          551528                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_miss_latency   7735952636                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_rate     0.063808                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_misses        142604                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency    526042500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.avg_blocked_cycles_no_mshrs 13994.026145                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles_no_targets         5000                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_refs                  8.879315                       # Average number of references to valid blocks.
system.cpu1.dcache.blocked_no_mshrs             31364                       # number of cycles access was blocked
system.cpu1.dcache.blocked_no_targets               1                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles_no_mshrs    438908636                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles_no_targets         5000                       # number of cycles access was blocked
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.demand_accesses            5824407                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_avg_miss_latency 33113.411747                       # average overall miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency 22501.069662                       # average overall mshr miss latency
system.cpu1.dcache.demand_hits                4488065                       # number of demand (read+write) hits
system.cpu1.dcache.demand_miss_latency    44250842881                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_rate          0.229438                       # miss rate for demand accesses
system.cpu1.dcache.demand_misses              1336342                       # number of demand (read+write) misses
system.cpu1.dcache.demand_mshr_hits            762669                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_miss_latency  12908256136                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_rate     0.098495                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_misses          573673                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.overall_accesses           5824407                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_avg_miss_latency 33113.411747                       # average overall miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency 22501.069662                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_hits               4488065                       # number of overall hits
system.cpu1.dcache.overall_miss_latency   44250842881                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_rate         0.229438                       # miss rate for overall accesses
system.cpu1.dcache.overall_misses             1336342                       # number of overall misses
system.cpu1.dcache.overall_mshr_hits           762669                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_miss_latency  12908256136                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_rate     0.098495                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_misses         573673                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_uncacheable_latency    824622000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.replacements                531784                       # number of replacements
system.cpu1.dcache.sampled_refs                532296                       # Sample count of references to valid blocks.
system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu1.dcache.tagsinuse               487.083551                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                 4726424                       # Total number of references to valid blocks.
system.cpu1.dcache.warmup_cycle           39405721000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.writebacks                  158239                       # number of writebacks
system.cpu1.decode.DECODE:BlockedCycles      17789626                       # Number of cycles decode is blocked
system.cpu1.decode.DECODE:BranchMispred         18017                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DECODE:BranchResolved       246498                       # Number of times decode resolved a branch
system.cpu1.decode.DECODE:DecodedInsts       26253438                       # Number of instructions handled by decode
system.cpu1.decode.DECODE:IdleCycles         14731458                       # Number of cycles decode is idle
system.cpu1.decode.DECODE:RunCycles           4724229                       # Number of cycles decode is running
system.cpu1.decode.DECODE:SquashCycles         641522                       # Number of cycles decode is squashing
system.cpu1.decode.DECODE:SquashedInsts         52769                       # Number of squashed instructions handled by decode
system.cpu1.decode.DECODE:UnblockCycles        232141                       # Number of cycles decode is unblocking
system.cpu1.dtb.accesses                       433929                       # DTB accesses
system.cpu1.dtb.acv                                77                       # DTB access violations
system.cpu1.dtb.hits                          6280849                       # DTB hits
system.cpu1.dtb.misses                          17153                       # DTB misses
system.cpu1.dtb.read_accesses                  314117                       # DTB read accesses
system.cpu1.dtb.read_acv                           13                       # DTB read access violations
system.cpu1.dtb.read_hits                     3872885                       # DTB read hits
system.cpu1.dtb.read_misses                     13436                       # DTB read misses
system.cpu1.dtb.write_accesses                 119812                       # DTB write accesses
system.cpu1.dtb.write_acv                          64                       # DTB write access violations
system.cpu1.dtb.write_hits                    2407964                       # DTB write hits
system.cpu1.dtb.write_misses                     3717                       # DTB write misses
system.cpu1.fetch.Branches                    5538388                       # Number of branches that fetch encountered
system.cpu1.fetch.CacheLines                  3089103                       # Number of cache lines fetched
system.cpu1.fetch.Cycles                      8137043                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.IcacheSquashes               192735                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.Insts                      26826541                       # Number of instructions fetch has processed
system.cpu1.fetch.MiscStallCycles                1090                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.SquashCycles                 373513                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.branchRate                 0.129267                       # Number of branch fetches per cycle
system.cpu1.fetch.icacheStallCycles           3089103                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.predictedBranches           2688799                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.rate                       0.626136                       # Number of inst fetches per cycle
system.cpu1.fetch.rateDist.start_dist                          # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist.samples           38118977                      
system.cpu1.fetch.rateDist.min_value                0                      
                               0     33077956   8677.56%           
                               1       338219     88.73%           
                               2       684572    179.59%           
                               3       401330    105.28%           
                               4       792380    207.87%           
                               5       254419     66.74%           
                               6       341251     89.52%           
                               7       404733    106.18%           
                               8      1824117    478.53%           
system.cpu1.fetch.rateDist.max_value                8                      
system.cpu1.fetch.rateDist.end_dist

system.cpu1.icache.ReadReq_accesses           3089103                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_avg_miss_latency 14554.963245                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11604.753460                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_hits               2620972                       # number of ReadReq hits
system.cpu1.icache.ReadReq_miss_latency    6813629499                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_rate         0.151543                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_misses              468131                       # number of ReadReq misses
system.cpu1.icache.ReadReq_mshr_hits            20962                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_miss_latency   5189286000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate     0.144757                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_misses         447169                       # number of ReadReq MSHR misses
system.cpu1.icache.avg_blocked_cycles_no_mshrs 11057.692308                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu1.icache.avg_refs                  5.861938                       # Average number of references to valid blocks.
system.cpu1.icache.blocked_no_mshrs                26                       # number of cycles access was blocked
system.cpu1.icache.blocked_no_targets               0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles_no_mshrs       287500                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.demand_accesses            3089103                       # number of demand (read+write) accesses
system.cpu1.icache.demand_avg_miss_latency 14554.963245                       # average overall miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency 11604.753460                       # average overall mshr miss latency
system.cpu1.icache.demand_hits                2620972                       # number of demand (read+write) hits
system.cpu1.icache.demand_miss_latency     6813629499                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_rate          0.151543                       # miss rate for demand accesses
system.cpu1.icache.demand_misses               468131                       # number of demand (read+write) misses
system.cpu1.icache.demand_mshr_hits             20962                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_miss_latency   5189286000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_rate     0.144757                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_misses          447169                       # number of demand (read+write) MSHR misses
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.overall_accesses           3089103                       # number of overall (read+write) accesses
system.cpu1.icache.overall_avg_miss_latency 14554.963245                       # average overall miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency 11604.753460                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_hits               2620972                       # number of overall hits
system.cpu1.icache.overall_miss_latency    6813629499                       # number of overall miss cycles
system.cpu1.icache.overall_miss_rate         0.151543                       # miss rate for overall accesses
system.cpu1.icache.overall_misses              468131                       # number of overall misses
system.cpu1.icache.overall_mshr_hits            20962                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_miss_latency   5189286000                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_rate     0.144757                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_misses         447169                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu1.icache.replacements                446606                       # number of replacements
system.cpu1.icache.sampled_refs                447117                       # Sample count of references to valid blocks.
system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu1.icache.tagsinuse               504.476148                       # Cycle average of tags in use
system.cpu1.icache.total_refs                 2620972                       # Total number of references to valid blocks.
system.cpu1.icache.warmup_cycle           54243392000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.writebacks                       0                       # number of writebacks
system.cpu1.idleCycles                        4725605                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.iew.EXEC:branches                 3215748                       # Number of branches executed
system.cpu1.iew.EXEC:nop                      1316352                       # number of nop insts executed
system.cpu1.iew.EXEC:rate                    0.474711                       # Inst execution rate
system.cpu1.iew.EXEC:refs                     6453696                       # number of memory reference insts executed
system.cpu1.iew.EXEC:stores                   2419389                       # Number of stores executed
system.cpu1.iew.EXEC:swp                            0                       # number of swp insts executed
system.cpu1.iew.WB:consumers                 12378269                       # num instructions consuming a value
system.cpu1.iew.WB:count                     20082329                       # cumulative count of insts written-back
system.cpu1.iew.WB:fanout                    0.731659                       # average fanout of values written-back
system.cpu1.iew.WB:penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.WB:penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.iew.WB:producers                  9056670                       # num instructions producing a value
system.cpu1.iew.WB:rate                      0.468725                       # insts written-back per cycle
system.cpu1.iew.WB:sent                      20124761                       # cumulative count of insts sent to commit
system.cpu1.iew.branchMispredicts              338961                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewBlockCycles                2501198                       # Number of cycles IEW is blocking
system.cpu1.iew.iewDispLoadInsts              4247428                       # Number of dispatched load instructions
system.cpu1.iew.iewDispNonSpecInsts            782465                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewDispSquashedInsts           352902                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispStoreInsts             2557361                       # Number of dispatched store instructions
system.cpu1.iew.iewDispatchedInsts           23476813                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewExecLoadInsts              4034307                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts           224585                       # Number of squashed instructions skipped in execute
system.cpu1.iew.iewExecutedInsts             20338799                       # Number of executed instructions
system.cpu1.iew.iewIQFullEvents                 13271                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewLSQFullEvents                 2314                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.iewSquashCycles                641522                       # Number of cycles IEW is squashing
system.cpu1.iew.iewUnblockCycles                92599                       # Number of cycles IEW is unblocking
system.cpu1.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread.0.cacheBlocked        96430                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.lsq.thread.0.forwLoads         136935                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread.0.ignoredResponses         5812                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread.0.memOrderViolation        18288                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread.0.rescheduledLoads         7650                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread.0.squashedLoads       696351                       # Number of loads squashed
system.cpu1.iew.lsq.thread.0.squashedStores       246865                       # Number of stores squashed
system.cpu1.iew.memOrderViolationEvents         18288                       # Number of memory order violations
system.cpu1.iew.predictedNotTakenIncorrect       160561                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.predictedTakenIncorrect        178400                       # Number of branches that were predicted taken incorrectly
system.cpu1.ipc                              0.432490                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.432490                       # IPC: Total IPC of All Threads
system.cpu1.iq.ISSUE:FU_type_0               20563386                       # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0.start_dist
                      No_OpClass         3984      0.02%            # Type of FU issued
                          IntAlu     13476321     65.54%            # Type of FU issued
                         IntMult        28965      0.14%            # Type of FU issued
                          IntDiv            0      0.00%            # Type of FU issued
                        FloatAdd        13702      0.07%            # Type of FU issued
                        FloatCmp            0      0.00%            # Type of FU issued
                        FloatCvt            0      0.00%            # Type of FU issued
                       FloatMult            0      0.00%            # Type of FU issued
                        FloatDiv         1986      0.01%            # Type of FU issued
                       FloatSqrt            0      0.00%            # Type of FU issued
                         MemRead      4173926     20.30%            # Type of FU issued
                        MemWrite      2443261     11.88%            # Type of FU issued
                       IprAccess       421241      2.05%            # Type of FU issued
                    InstPrefetch            0      0.00%            # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0.end_dist
system.cpu1.iq.ISSUE:fu_busy_cnt               221052                       # FU busy when requested
system.cpu1.iq.ISSUE:fu_busy_rate            0.010750                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.ISSUE:fu_full.start_dist
                      No_OpClass            0      0.00%            # attempts to use FU when none available
                          IntAlu        16139      7.30%            # attempts to use FU when none available
                         IntMult            0      0.00%            # attempts to use FU when none available
                          IntDiv            0      0.00%            # attempts to use FU when none available
                        FloatAdd            0      0.00%            # attempts to use FU when none available
                        FloatCmp            0      0.00%            # attempts to use FU when none available
                        FloatCvt            0      0.00%            # attempts to use FU when none available
                       FloatMult            0      0.00%            # attempts to use FU when none available
                        FloatDiv            0      0.00%            # attempts to use FU when none available
                       FloatSqrt            0      0.00%            # attempts to use FU when none available
                         MemRead       131915     59.68%            # attempts to use FU when none available
                        MemWrite        72998     33.02%            # attempts to use FU when none available
                       IprAccess            0      0.00%            # attempts to use FU when none available
                    InstPrefetch            0      0.00%            # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full.end_dist
system.cpu1.iq.ISSUE:issued_per_cycle.start_dist                     # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle.samples     38118977                      
system.cpu1.iq.ISSUE:issued_per_cycle.min_value            0                      
                               0     28405823   7451.88%           
                               1      4664380   1223.64%           
                               2      1989669    521.96%           
                               3      1362790    357.51%           
                               4       979073    256.85%           
                               5       465618    122.15%           
                               6       186895     49.03%           
                               7        52286     13.72%           
                               8        12443      3.26%           
system.cpu1.iq.ISSUE:issued_per_cycle.max_value            8                      
system.cpu1.iq.ISSUE:issued_per_cycle.end_dist

system.cpu1.iq.ISSUE:rate                    0.479953                       # Inst issue rate
system.cpu1.iq.iqInstsAdded                  21283894                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqInstsIssued                 20563386                       # Number of instructions issued
system.cpu1.iq.iqNonSpecInstsAdded             876567                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqSquashedInstsExamined        3483485                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedInstsIssued            16725                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedNonSpecRemoved        620822                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.iqSquashedOperandsExamined      1773520                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.itb.accesses                       525294                       # ITB accesses
system.cpu1.itb.acv                               109                       # ITB acv
system.cpu1.itb.hits                           518481                       # ITB hits
system.cpu1.itb.misses                           6813                       # ITB misses
system.cpu1.kern.callpal                        87355                       # number of callpals executed
system.cpu1.kern.callpal_cserve                     1      0.00%      0.00% # number of callpals executed
system.cpu1.kern.callpal_wripir                    17      0.02%      0.02% # number of callpals executed
system.cpu1.kern.callpal_wrmces                     1      0.00%      0.02% # number of callpals executed
system.cpu1.kern.callpal_wrfen                      1      0.00%      0.02% # number of callpals executed
system.cpu1.kern.callpal_swpctx                  1838      2.10%      2.13% # number of callpals executed
system.cpu1.kern.callpal_tbi                        3      0.00%      2.13% # number of callpals executed
system.cpu1.kern.callpal_wrent                      7      0.01%      2.14% # number of callpals executed
system.cpu1.kern.callpal_swpipl                 79684     91.22%     93.36% # number of callpals executed
system.cpu1.kern.callpal_rdps                    2408      2.76%     96.11% # number of callpals executed
system.cpu1.kern.callpal_wrkgp                      1      0.00%     96.11% # number of callpals executed
system.cpu1.kern.callpal_wrusp                      4      0.00%     96.12% # number of callpals executed
system.cpu1.kern.callpal_whami                      3      0.00%     96.12% # number of callpals executed
system.cpu1.kern.callpal_rti                     3206      3.67%     99.79% # number of callpals executed
system.cpu1.kern.callpal_callsys                  136      0.16%     99.95% # number of callpals executed
system.cpu1.kern.callpal_imb                       44      0.05%    100.00% # number of callpals executed
system.cpu1.kern.callpal_rdunique                   1      0.00%    100.00% # number of callpals executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.hwrei                     93966                       # number of hwrei instructions executed
system.cpu1.kern.inst.quiesce                    3806                       # number of quiesce instructions executed
system.cpu1.kern.ipl_count                      84915                       # number of times we switched to this ipl
system.cpu1.kern.ipl_count_0                    34143     40.21%     40.21% # number of times we switched to this ipl
system.cpu1.kern.ipl_count_22                    1928      2.27%     42.48% # number of times we switched to this ipl
system.cpu1.kern.ipl_count_30                      96      0.11%     42.59% # number of times we switched to this ipl
system.cpu1.kern.ipl_count_31                   48748     57.41%    100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_good                       68760                       # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good_0                     33416     48.60%     48.60% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good_22                     1928      2.80%     51.40% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good_30                       96      0.14%     51.54% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good_31                    33320     48.46%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks               1907704531000                       # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks_0             1871986899500     98.13%     98.13% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks_22               352080000      0.02%     98.15% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks_30                40004500      0.00%     98.15% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks_31             35325547000      1.85%    100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used_0                  0.978707                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used_22                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used_30                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used_31                 0.683515                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.mode_good_kernel                 521                      
system.cpu1.kern.mode_good_user                   463                      
system.cpu1.kern.mode_good_idle                    58                      
system.cpu1.kern.mode_switch_kernel              2305                       # number of protection mode switches
system.cpu1.kern.mode_switch_user                 463                       # number of protection mode switches
system.cpu1.kern.mode_switch_idle                2035                       # number of protection mode switches
system.cpu1.kern.mode_switch_good            1.254532                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good_kernel     0.226030                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good_user              1                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good_idle       0.028501                       # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks_kernel        46750182500      2.45%      2.45% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks_user           1015923000      0.05%      2.50% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks_idle         1859938417500     97.50%    100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context                    1839                       # number of times the context was actually changed
system.cpu1.kern.syscall                          104                       # number of syscalls executed
system.cpu1.kern.syscall_3                         11     10.58%     10.58% # number of syscalls executed
system.cpu1.kern.syscall_6                         10      9.62%     20.19% # number of syscalls executed
system.cpu1.kern.syscall_15                         1      0.96%     21.15% # number of syscalls executed
system.cpu1.kern.syscall_17                         6      5.77%     26.92% # number of syscalls executed
system.cpu1.kern.syscall_23                         3      2.88%     29.81% # number of syscalls executed
system.cpu1.kern.syscall_24                         3      2.88%     32.69% # number of syscalls executed
system.cpu1.kern.syscall_33                         4      3.85%     36.54% # number of syscalls executed
system.cpu1.kern.syscall_45                        18     17.31%     53.85% # number of syscalls executed
system.cpu1.kern.syscall_47                         3      2.88%     56.73% # number of syscalls executed
system.cpu1.kern.syscall_59                         1      0.96%     57.69% # number of syscalls executed
system.cpu1.kern.syscall_71                        31     29.81%     87.50% # number of syscalls executed
system.cpu1.kern.syscall_74                        10      9.62%     97.12% # number of syscalls executed
system.cpu1.kern.syscall_132                        3      2.88%    100.00% # number of syscalls executed
system.cpu1.numCycles                        42844582                       # number of cpu cycles simulated
system.cpu1.rename.RENAME:BlockCycles         3655834                       # Number of cycles rename is blocking
system.cpu1.rename.RENAME:CommittedMaps      13191652                       # Number of HB maps that are committed
system.cpu1.rename.RENAME:IQFullEvents         331503                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.RENAME:IdleCycles         15199760                       # Number of cycles rename is idle
system.cpu1.rename.RENAME:LSQFullEvents        648645                       # Number of times rename has blocked due to LSQ full
system.cpu1.rename.RENAME:ROBFullEvents          1226                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.RENAME:RenameLookups      29419469                       # Number of register rename lookups that rename has made
system.cpu1.rename.RENAME:RenamedInsts       24525114                       # Number of instructions processed by rename
system.cpu1.rename.RENAME:RenamedOperands     16182590                       # Number of destination operands rename has renamed
system.cpu1.rename.RENAME:RunCycles           4333684                       # Number of cycles rename is running
system.cpu1.rename.RENAME:SquashCycles         641522                       # Number of cycles rename is squashing
system.cpu1.rename.RENAME:UnblockCycles       1812010                       # Number of cycles rename is unblocking
system.cpu1.rename.RENAME:UndoneMaps          2990936                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.RENAME:serializeStallCycles     12476165                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RENAME:serializingInsts       728375                       # count of serializing insts renamed
system.cpu1.rename.RENAME:skidInsts           4962161                       # count of insts added to the skid buffer
system.cpu1.rename.RENAME:tempSerializingInsts        86287                       # count of temporary serializing insts renamed
system.cpu1.timesIdled                         480520                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.iocache.ReadReq_accesses                   175                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_avg_miss_latency  115331.417143                       # average ReadReq miss latency
system.iocache.ReadReq_avg_mshr_miss_latency 63331.417143                       # average ReadReq mshr miss latency
system.iocache.ReadReq_miss_latency          20182998                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_rate                    1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_misses                     175                       # number of ReadReq misses
system.iocache.ReadReq_mshr_miss_latency     11082998                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate               1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_misses                175                       # number of ReadReq MSHR misses
system.iocache.WriteReq_accesses                41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_avg_miss_latency 137844.166490                       # average WriteReq miss latency
system.iocache.WriteReq_avg_mshr_miss_latency 85840.579852                       # average WriteReq mshr miss latency
system.iocache.WriteReq_miss_latency       5727700806                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_rate                   1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_misses                  41552                       # number of WriteReq misses
system.iocache.WriteReq_mshr_miss_latency   3566847774                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_rate              1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_misses             41552                       # number of WriteReq MSHR misses
system.iocache.avg_blocked_cycles_no_mshrs  6165.982406                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.blocked_no_mshrs                 10458                       # number of cycles access was blocked
system.iocache.blocked_no_targets                   0                       # number of cycles access was blocked
system.iocache.blocked_cycles_no_mshrs       64483844                       # number of cycles access was blocked
system.iocache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.demand_accesses                  41727                       # number of demand (read+write) accesses
system.iocache.demand_avg_miss_latency   137749.749658                       # average overall miss latency
system.iocache.demand_avg_mshr_miss_latency 85746.178062                       # average overall mshr miss latency
system.iocache.demand_hits                          0                       # number of demand (read+write) hits
system.iocache.demand_miss_latency         5747883804                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_rate                     1                       # miss rate for demand accesses
system.iocache.demand_misses                    41727                       # number of demand (read+write) misses
system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
system.iocache.demand_mshr_miss_latency    3577930772                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_rate                1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_misses               41727                       # number of demand (read+write) MSHR misses
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.iocache.overall_accesses                 41727                       # number of overall (read+write) accesses
system.iocache.overall_avg_miss_latency  137749.749658                       # average overall miss latency
system.iocache.overall_avg_mshr_miss_latency 85746.178062                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.iocache.overall_hits                         0                       # number of overall hits
system.iocache.overall_miss_latency        5747883804                       # number of overall miss cycles
system.iocache.overall_miss_rate                    1                       # miss rate for overall accesses
system.iocache.overall_misses                   41727                       # number of overall misses
system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
system.iocache.overall_mshr_miss_latency   3577930772                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_rate               1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_misses              41727                       # number of overall MSHR misses
system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.iocache.replacements                     41697                       # number of replacements
system.iocache.sampled_refs                     41713                       # Sample count of references to valid blocks.
system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
system.iocache.tagsinuse                     0.387817                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.warmup_cycle              1717170531000                       # Cycle when the warmup percentage was hit.
system.iocache.writebacks                       41522                       # number of writebacks
system.l2c.ReadExReq_accesses                  317502                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_avg_miss_latency    52375.567080                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency 40223.034620                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_miss_latency         16629347299                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_rate                      1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_misses                    317502                       # number of ReadExReq misses
system.l2c.ReadExReq_mshr_miss_latency    12770893938                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_rate                 1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_misses               317502                       # number of ReadExReq MSHR misses
system.l2c.ReadReq_accesses                   2204255                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_avg_miss_latency      52067.361570                       # average ReadReq miss latency
system.l2c.ReadReq_avg_mshr_miss_latency 40026.445360                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_hits                       1893900                       # number of ReadReq hits
system.l2c.ReadReq_miss_latency           16159366000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_rate                 0.140798                       # miss rate for ReadReq accesses
system.l2c.ReadReq_misses                      310355                       # number of ReadReq misses
system.l2c.ReadReq_mshr_hits                       17                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_miss_latency      12421727000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_rate            0.140790                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_misses                 310338                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_uncacheable_latency    840472000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.UpgradeReq_accesses                 141949                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_avg_miss_latency   51066.182164                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency 40093.287026                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_miss_latency         7248793492                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_rate                     1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_misses                   141949                       # number of UpgradeReq misses
system.l2c.UpgradeReq_mshr_miss_latency    5691202000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_rate                1                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_misses              141949                       # number of UpgradeReq MSHR misses
system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_mshr_uncacheable_latency   1423764498                       # number of WriteReq MSHR uncacheable cycles
system.l2c.Writeback_accesses                  455578                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_hits                      455578                       # number of Writeback hits
system.l2c.avg_blocked_cycles_no_mshrs   <err: div-0>                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.l2c.avg_refs                          4.834791                       # Average number of references to valid blocks.
system.l2c.blocked_no_mshrs                         0                       # number of cycles access was blocked
system.l2c.blocked_no_targets                       0                       # number of cycles access was blocked
system.l2c.blocked_cycles_no_mshrs                  0                       # number of cycles access was blocked
system.l2c.blocked_cycles_no_targets                0                       # number of cycles access was blocked
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.demand_accesses                    2521757                       # number of demand (read+write) accesses
system.l2c.demand_avg_miss_latency       52223.218502                       # average overall miss latency
system.l2c.demand_avg_mshr_miss_latency  40125.861586                       # average overall mshr miss latency
system.l2c.demand_hits                        1893900                       # number of demand (read+write) hits
system.l2c.demand_miss_latency            32788713299                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_rate                  0.248976                       # miss rate for demand accesses
system.l2c.demand_misses                       627857                       # number of demand (read+write) misses
system.l2c.demand_mshr_hits                        17                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_miss_latency       25192620938                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_rate             0.248969                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_misses                  627840                       # number of demand (read+write) MSHR misses
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.l2c.overall_accesses                   2521757                       # number of overall (read+write) accesses
system.l2c.overall_avg_miss_latency      52223.218502                       # average overall miss latency
system.l2c.overall_avg_mshr_miss_latency 40125.861586                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.l2c.overall_hits                       1893900                       # number of overall hits
system.l2c.overall_miss_latency           32788713299                       # number of overall miss cycles
system.l2c.overall_miss_rate                 0.248976                       # miss rate for overall accesses
system.l2c.overall_misses                      627857                       # number of overall misses
system.l2c.overall_mshr_hits                       17                       # number of overall MSHR hits
system.l2c.overall_mshr_miss_latency      25192620938                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_rate            0.248969                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_misses                 627840                       # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_latency   2264236498                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.l2c.replacements                        402142                       # number of replacements
system.l2c.sampled_refs                        433669                       # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
system.l2c.tagsinuse                     31163.178814                       # Cycle average of tags in use
system.l2c.total_refs                         2096699                       # Total number of references to valid blocks.
system.l2c.warmup_cycle                    9278348000                       # Cycle when the warmup percentage was hit.
system.l2c.writebacks                          124293                       # number of writebacks
system.tsunami.ethernet.coalescedRxDesc  <err: div-0>                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.coalescedRxIdle  <err: div-0>                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.coalescedRxOk    <err: div-0>                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.coalescedRxOrn   <err: div-0>                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.coalescedSwi     <err: div-0>                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.coalescedTotal   <err: div-0>                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.coalescedTxDesc  <err: div-0>                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.coalescedTxIdle  <err: div-0>                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.coalescedTxOk    <err: div-0>                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR

---------- End Simulation Statistics   ----------