path: root/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.582520                       # Number of seconds simulated
sim_ticks                                2582520130500                       # Number of ticks simulated
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  84908                       # Simulator instruction rate (inst/s)
host_tick_rate                             2745493933                       # Simulator tick rate (ticks/s)
host_mem_usage                                 385348                       # Number of bytes of host memory used
host_seconds                                   940.64                       # Real time elapsed on the host
sim_insts                                    79867485                       # Number of instructions simulated
system.l2c.replacements                        132224                       # number of replacements
system.l2c.tagsinuse                     27582.981749                       # Cycle average of tags in use
system.l2c.total_refs                         1821382                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        162180                       # Sample count of references to valid blocks.
system.l2c.avg_refs                         11.230620                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::0                  5000.765535                       # Average occupied blocks per context
system.l2c.occ_blocks::1                  7177.119061                       # Average occupied blocks per context
system.l2c.occ_blocks::2                 15405.097153                       # Average occupied blocks per context
system.l2c.occ_percent::0                    0.076306                       # Average percentage of cache occupancy
system.l2c.occ_percent::1                    0.109514                       # Average percentage of cache occupancy
system.l2c.occ_percent::2                    0.235063                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::0                     739666                       # number of ReadReq hits
system.l2c.ReadReq_hits::1                     629011                       # number of ReadReq hits
system.l2c.ReadReq_hits::2                     183263                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1551940                       # number of ReadReq hits
system.l2c.Writeback_hits::0                   599118                       # number of Writeback hits
system.l2c.Writeback_hits::total               599118                       # number of Writeback hits
system.l2c.UpgradeReq_hits::0                    1040                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::1                    1060                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                2100                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::0                   181                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::1                   449                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total               630                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::0                    58369                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::1                    39072                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                97441                       # number of ReadExReq hits
system.l2c.demand_hits::0                      798035                       # number of demand (read+write) hits
system.l2c.demand_hits::1                      668083                       # number of demand (read+write) hits
system.l2c.demand_hits::2                      183263                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1649381                       # number of demand (read+write) hits
system.l2c.overall_hits::0                     798035                       # number of overall hits
system.l2c.overall_hits::1                     668083                       # number of overall hits
system.l2c.overall_hits::2                     183263                       # number of overall hits
system.l2c.overall_hits::total                1649381                       # number of overall hits
system.l2c.ReadReq_misses::0                    19689                       # number of ReadReq misses
system.l2c.ReadReq_misses::1                    20600                       # number of ReadReq misses
system.l2c.ReadReq_misses::2                      170                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                40459                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::0                  7392                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::1                  3836                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             11228                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::0                 864                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::1                 461                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1325                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::0                  98007                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::1                  50222                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             148229                       # number of ReadExReq misses
system.l2c.demand_misses::0                    117696                       # number of demand (read+write) misses
system.l2c.demand_misses::1                     70822                       # number of demand (read+write) misses
system.l2c.demand_misses::2                       170                       # number of demand (read+write) misses
system.l2c.demand_misses::total                188688                       # number of demand (read+write) misses
system.l2c.overall_misses::0                   117696                       # number of overall misses
system.l2c.overall_misses::1                    70822                       # number of overall misses
system.l2c.overall_misses::2                      170                       # number of overall misses
system.l2c.overall_misses::total               188688                       # number of overall misses
system.l2c.ReadReq_miss_latency            2113875000                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency           61547500                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency          8091500                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency          7780940999                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency             9894815999                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency            9894815999                       # number of overall miss cycles
system.l2c.ReadReq_accesses::0                 759355                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::1                 649611                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::2                 183433                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1592399                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::0               599118                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           599118                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::0                8432                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::1                4896                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           13328                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::0              1045                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::1               910                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          1955                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::0               156376                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::1                89294                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           245670                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::0                  915731                       # number of demand (read+write) accesses
system.l2c.demand_accesses::1                  738905                       # number of demand (read+write) accesses
system.l2c.demand_accesses::2                  183433                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             1838069                       # number of demand (read+write) accesses
system.l2c.overall_accesses::0                 915731                       # number of overall (read+write) accesses
system.l2c.overall_accesses::1                 738905                       # number of overall (read+write) accesses
system.l2c.overall_accesses::2                 183433                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            1838069                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::0              0.025929                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::1              0.031711                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::2              0.000927                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.058567                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::0           0.876660                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::1           0.783497                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::0         0.826794                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::1         0.506593                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::0            0.626739                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::1            0.562434                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::0               0.128527                       # miss rate for demand accesses
system.l2c.demand_miss_rate::1               0.095847                       # miss rate for demand accesses
system.l2c.demand_miss_rate::2               0.000927                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.225301                       # miss rate for demand accesses
system.l2c.overall_miss_rate::0              0.128527                       # miss rate for overall accesses
system.l2c.overall_miss_rate::1              0.095847                       # miss rate for overall accesses
system.l2c.overall_miss_rate::2              0.000927                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.225301                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::0   107363.248514                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::1   102615.291262                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::2   12434558.823529                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 12644537.363306                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::0  8326.231061                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::1 16044.708029                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::2          inf                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::0  9365.162037                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::1 17552.060738                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::2          inf                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total          inf                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::0 79391.686298                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::1 154930.926666                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::2          inf                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::0    84070.962471                       # average overall miss latency
system.l2c.demand_avg_miss_latency::1    139713.874206                       # average overall miss latency
system.l2c.demand_avg_miss_latency::2    58204799.994118                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 58428584.830795                       # average overall miss latency
system.l2c.overall_avg_miss_latency::0   84070.962471                       # average overall miss latency
system.l2c.overall_avg_miss_latency::1   139713.874206                       # average overall miss latency
system.l2c.overall_avg_miss_latency::2   58204799.994118                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 58428584.830795                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks                          112853                       # number of writebacks
system.l2c.ReadReq_mshr_hits                       94                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits                        94                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits                       94                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses                  40365                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses               11228                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses              1325                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses               148229                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses                  188594                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses                 188594                       # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency       1617473000                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency     449580000                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency     53034500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency     5939516999                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency        7556989999                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency       7556989999                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency 131965465500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency  32542103084                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency 164507568584                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::0         0.053157                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::1         0.062137                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::2         0.220053                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.335347                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::0      1.331594                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::1      2.293301                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::2           inf                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::0     1.267943                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::1     1.456044                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::2          inf                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::0       0.947901                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::1       1.660011                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::2            inf                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::0          0.205949                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::1          0.255234                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::2          1.028136                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      1.489319                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::0         0.205949                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::1         0.255234                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::2         1.028136                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     1.489319                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency 40071.175523                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency 40040.969006                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40026.037736                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency 40069.871611                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency  40070.150689                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency 40070.150689                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    42414340                       # DTB read hits
system.cpu0.dtb.read_misses                     56223                       # DTB read misses
system.cpu0.dtb.write_hits                    6898086                       # DTB write hits
system.cpu0.dtb.write_misses                    11305                       # DTB write misses
system.cpu0.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    2713                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                    11513                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                   590                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                     1641                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                42470563                       # DTB read accesses
system.cpu0.dtb.write_accesses                6909391                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         49312426                       # DTB hits
system.cpu0.dtb.misses                          67528                       # DTB misses
system.cpu0.dtb.accesses                     49379954                       # DTB accesses
system.cpu0.itb.inst_hits                     6438737                       # ITB inst hits
system.cpu0.itb.inst_misses                     18334                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    1587                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     6092                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                 6457071                       # ITB inst accesses
system.cpu0.itb.hits                          6438737                       # DTB hits
system.cpu0.itb.misses                          18334                       # DTB misses
system.cpu0.itb.accesses                      6457071                       # DTB accesses
system.cpu0.numCycles                       352502516                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.BPredUnit.lookups                 8652992                       # Number of BP lookups
system.cpu0.BPredUnit.condPredicted           6404778                       # Number of conditional branches predicted
system.cpu0.BPredUnit.condIncorrect            637693                       # Number of conditional branches incorrect
system.cpu0.BPredUnit.BTBLookups              7363134                       # Number of BTB lookups
system.cpu0.BPredUnit.BTBHits                 5053345                       # Number of BTB hits
system.cpu0.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.BPredUnit.usedRAS                  807352                       # Number of times the RAS was used to get a target.
system.cpu0.BPredUnit.RASInCorrect             136692                       # Number of incorrect RAS predictions.
system.cpu0.fetch.icacheStallCycles          16884109                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                      45966993                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                    8652992                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches           5860697                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                     11522341                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                2668103                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                    112168                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.BlockedCycles              79167270                       # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles                2014                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles       119305                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       115037                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles          246                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                  6432455                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               291981                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                   9711                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples         109779148                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             0.541337                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            1.795461                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                98275003     89.52%     89.52% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                 1141137      1.04%     90.56% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                 1489424      1.36%     91.92% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                 1304085      1.19%     93.10% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                 1112037      1.01%     94.12% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                  879763      0.80%     94.92% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                  783842      0.71%     95.63% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                  505631      0.46%     96.09% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 4288226      3.91%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total           109779148                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.024547                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.130402                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                18050945                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             78849390                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                 10366657                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles               743574                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               1768582                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved             1352275                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred                89418                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              56923097                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts               298418                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               1768582                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                19113011                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles               33326039                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      41047359                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                 10060323                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles              4463834                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              54560689                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                 1472                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents                580904                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents              3150021                       # Number of times rename has blocked due to LSQ full
system.cpu0.rename.FullRegisterEvents             227                       # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands           54846534                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups            247844774                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups       247794895                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups            49879                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             41443860                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                13402673                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts            827250                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts        762254                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                  8494444                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads            11787351                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores            7696820                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1444181                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         1562010                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  51022975                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded            1296408                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 80307756                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued           139273                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined        9946263                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     22977035                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        252908                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples    109779148                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.731539                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.440195                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           80155628     73.02%     73.02% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1           10112206      9.21%     82.23% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            4137187      3.77%     86.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            3171994      2.89%     88.88% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            9961890      9.07%     97.96% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5            1265964      1.15%     99.11% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6             671041      0.61%     99.72% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             224336      0.20%     99.93% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8              78902      0.07%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total      109779148                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                  37945      0.47%      0.47% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                   630      0.01%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead               7705227     95.96%     96.44% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               285473      3.56%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass            88461      0.11%      0.11% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             29747563     37.04%     37.15% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               62367      0.08%     37.23% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     37.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     37.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     37.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     37.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     37.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     37.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     37.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     37.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     37.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     37.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     37.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     37.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  5      0.00%     37.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     37.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     37.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 4      0.00%     37.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              4      0.00%     37.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     37.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     37.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     37.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     37.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     37.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     37.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc          1707      0.00%     37.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     37.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            4      0.00%     37.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     37.23% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead            43146000     53.73%     90.96% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite            7261641      9.04%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              80307756                       # Type of FU issued
system.cpu0.iq.rate                          0.227822                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                    8029275                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.099981                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         278618763                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         62278383                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     46688761                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads              11606                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes              7153                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses         5243                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              88242529                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                   6041                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          399833                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      2542386                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         5153                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        20600                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores      1003035                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads     32220164                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked        13264                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               1768582                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles               25955516                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles               355771                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           52493661                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts           246498                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts             11787351                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts             7696820                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts            864266                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 62537                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                 5227                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         20600                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        509776                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       136927                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              646703                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             79579333                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts             42855337                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           728423                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       174278                       # number of nop insts executed
system.cpu0.iew.exec_refs                    50025973                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                 6436853                       # Number of branches executed
system.cpu0.iew.exec_stores                   7170636                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.225755                       # Inst execution rate
system.cpu0.iew.wb_sent                      79157088                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     46694004                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 24804627                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 46107956                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.132464                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.537968                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitCommittedInsts      41930270                       # The number of committed instructions
system.cpu0.commit.commitSquashedInsts       10408005                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls        1043500                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           570177                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples    108054182                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.388049                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.248702                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     91026362     84.24%     84.24% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1      9315133      8.62%     92.86% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      2453841      2.27%     95.13% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      1345650      1.25%     96.38% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4      1029771      0.95%     97.33% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       653477      0.60%     97.94% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6       658529      0.61%     98.55% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       238490      0.22%     98.77% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1332929      1.23%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total    108054182                       # Number of insts commited each cycle
system.cpu0.commit.count                     41930270                       # Number of instructions committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      15938750                       # Number of memory references committed
system.cpu0.commit.loads                      9244965                       # Number of loads committed
system.cpu0.commit.membars                     288660                       # Number of memory barriers committed
system.cpu0.commit.branches                   5543054                       # Number of branches committed
system.cpu0.commit.fp_insts                      4980                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 37176133                       # Number of committed integer instructions.
system.cpu0.commit.function_calls              620334                       # Number of function calls committed.
system.cpu0.commit.bw_lim_events              1332929                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                   157975997                       # The number of ROB reads
system.cpu0.rob.rob_writes                  106454954                       # The number of ROB writes
system.cpu0.timesIdled                        1454281                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                      242723368                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.committedInsts                   41804443                       # Number of Instructions Simulated
system.cpu0.committedInsts_total             41804443                       # Number of Instructions Simulated
system.cpu0.cpi                              8.432178                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        8.432178                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.118593                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.118593                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads               354304839                       # number of integer regfile reads
system.cpu0.int_regfile_writes               46156049                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                     4230                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                    1342                       # number of floating regfile writes
system.cpu0.misc_regfile_reads               65708495                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                636034                       # number of misc regfile writes
system.cpu0.icache.replacements                540132                       # number of replacements
system.cpu0.icache.tagsinuse               511.623908                       # Cycle average of tags in use
system.cpu0.icache.total_refs                 5846805                       # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs                540644                       # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs                 10.814519                       # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle           16020223000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::0           511.623908                       # Average occupied blocks per context
system.cpu0.icache.occ_percent::0            0.999265                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::0            5846805                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total        5846805                       # number of ReadReq hits
system.cpu0.icache.demand_hits::0             5846805                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::1                   0                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total         5846805                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::0            5846805                       # number of overall hits
system.cpu0.icache.overall_hits::1                  0                       # number of overall hits
system.cpu0.icache.overall_hits::total        5846805                       # number of overall hits
system.cpu0.icache.ReadReq_misses::0           585522                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       585522                       # number of ReadReq misses
system.cpu0.icache.demand_misses::0            585522                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::1                 0                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        585522                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::0           585522                       # number of overall misses
system.cpu0.icache.overall_misses::1                0                       # number of overall misses
system.cpu0.icache.overall_misses::total       585522                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency    8762208993                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency     8762208993                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency    8762208993                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::0        6432327                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total      6432327                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::0         6432327                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total      6432327                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::0        6432327                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total      6432327                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::0      0.091028                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::0       0.091028                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::0      0.091028                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::0 14964.781841                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::0 14964.781841                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::0 14964.781841                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs      1480495                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              196                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs  7553.545918                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.writebacks                   29912                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits            44859                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits             44859                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits            44859                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses         540663                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses          540663                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses         540663                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency   6562850995                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency   6562850995                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency   6562850995                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency      6685500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency      6685500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::0     0.084054                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::0     0.084054                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::0     0.084054                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12138.524358                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency 12138.524358                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency 12138.524358                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.replacements                372646                       # number of replacements
system.cpu0.dcache.tagsinuse               487.071508                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                12784845                       # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs                373158                       # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs                 34.261211                       # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle              49147000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::0           487.071508                       # Average occupied blocks per context
system.cpu0.dcache.occ_percent::0            0.951312                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::0            7969031                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        7969031                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::0           4348200                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       4348200                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::0       221332                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       221332                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::0        199760                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       199760                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::0            12317231                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        12317231                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::0           12317231                       # number of overall hits
system.cpu0.dcache.overall_hits::1                  0                       # number of overall hits
system.cpu0.dcache.overall_hits::total       12317231                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::0           463423                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       463423                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::0         1863605                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1863605                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::0         9962                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total         9962                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::0         7780                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total         7780                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::0           2327028                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       2327028                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::0          2327028                       # number of overall misses
system.cpu0.dcache.overall_misses::1                0                       # number of overall misses
system.cpu0.dcache.overall_misses::total      2327028                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency    6461559500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency  70508741836                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency    120808500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency     88519000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency    76970301336                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency   76970301336                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::0        8432454                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      8432454                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::0       6211805                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      6211805                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::0       231294                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       231294                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::0       207540                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       207540                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::0        14644259                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     14644259                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::0       14644259                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     14644259                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::0      0.054957                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::0     0.300010                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::0     0.043071                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::0     0.037487                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::0       0.158904                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::0      0.158904                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::0 13943.113527                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::0 37834.595763                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 12126.932343                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 11377.763496                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::0 33076.654572                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::0 33076.654572                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs      6713488                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets      1808000                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs              859                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets            123                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs  7815.469150                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 14699.186992                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks                  327128                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits           223214                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits         1685177                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits          329                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits           1908391                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits          1908391                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses         240209                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses        178428                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses         9633                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses         7778                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses          418637                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses         418637                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency   2943893000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency   6377983487                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency     86869500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency     65155000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency   9321876487                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency   9321876487                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 138959490000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency   1038770484                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency 139998260484                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::0     0.028486                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::0     0.028724                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0     0.041648                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0     0.037477                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::0     0.028587                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::0     0.028587                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 12255.548293                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 35745.418247                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency  9017.907194                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency  8376.832091                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency 22267.206403                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency 22267.206403                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    10576986                       # DTB read hits
system.cpu1.dtb.read_misses                     41991                       # DTB read misses
system.cpu1.dtb.write_hits                    5532460                       # DTB write hits
system.cpu1.dtb.write_misses                    15559                       # DTB write misses
system.cpu1.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    1928                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                     5132                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   260                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      787                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                10618977                       # DTB read accesses
system.cpu1.dtb.write_accesses                5548019                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         16109446                       # DTB hits
system.cpu1.dtb.misses                          57550                       # DTB misses
system.cpu1.dtb.accesses                     16166996                       # DTB accesses
system.cpu1.itb.inst_hits                     8208666                       # ITB inst hits
system.cpu1.itb.inst_misses                      3757                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    1369                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                     2255                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                 8212423                       # ITB inst accesses
system.cpu1.itb.hits                          8208666                       # DTB hits
system.cpu1.itb.misses                           3757                       # DTB misses
system.cpu1.itb.accesses                      8212423                       # DTB accesses
system.cpu1.numCycles                        69081256                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.BPredUnit.lookups                 8330796                       # Number of BP lookups
system.cpu1.BPredUnit.condPredicted           6738871                       # Number of conditional branches predicted
system.cpu1.BPredUnit.condIncorrect            503522                       # Number of conditional branches incorrect
system.cpu1.BPredUnit.BTBLookups              7267639                       # Number of BTB lookups
system.cpu1.BPredUnit.BTBHits                 5704343                       # Number of BTB hits
system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.BPredUnit.usedRAS                  683793                       # Number of times the RAS was used to get a target.
system.cpu1.BPredUnit.RASInCorrect             107847                       # Number of incorrect RAS predictions.
system.cpu1.fetch.icacheStallCycles          17620797                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                      62561411                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                    8330796                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches           6388136                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                     13917594                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                4639299                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                     49548                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.BlockedCycles              15790396                       # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles                3022                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles        34407                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles       125274                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles          237                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                  8206050                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes               760093                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                   2394                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples          50674659                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             1.494403                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.744832                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                36764920     72.55%     72.55% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                  704096      1.39%     73.94% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                 1222881      2.41%     76.35% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                 2516311      4.97%     81.32% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                 1142608      2.25%     83.57% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                  651052      1.28%     84.86% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                 1887369      3.72%     88.58% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                  403735      0.80%     89.38% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                 5381687     10.62%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total            50674659                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.120594                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.905621                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                18672830                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles             16053118                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                 12511393                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles               382905                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               3054413                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved             1082178                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred                80433                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              69756936                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts               260341                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               3054413                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                19817710                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                3624621                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles      10850261                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                 11740016                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles              1587638                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              63840108                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                 3002                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                319994                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents               862075                       # Number of times rename has blocked due to LSQ full
system.cpu1.rename.FullRegisterEvents           38212                       # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands           68266339                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            296265404                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups       296212618                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups            52786                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps             39108942                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                29157397                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts            433648                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts        381432                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                  4194062                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads            11085935                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores            7020391                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads           635108                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores          890373                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                  56044948                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded             651331                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                 50360925                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued           120514                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined       18223761                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined     52593424                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        131996                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples     50674659                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.993809                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.617399                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0           32153473     63.45%     63.45% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1            5526378     10.91%     74.36% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2            3775422      7.45%     81.81% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3            3611274      7.13%     88.93% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4            2989508      5.90%     94.83% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5            1557590      3.07%     97.91% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6             784960      1.55%     99.46% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7             214293      0.42%     99.88% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8              61761      0.12%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total       50674659                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                  15522      1.51%      1.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                  1191      0.12%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                749386     73.14%     74.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite               258502     25.23%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass            18622      0.04%      0.04% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu             32758484     65.05%     65.08% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               50347      0.10%     65.18% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     65.18% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     65.18% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     65.18% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     65.18% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     65.18% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     65.18% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     65.18% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     65.18% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     65.18% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     65.18% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     65.18% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     65.18% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  2      0.00%     65.18% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     65.18% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     65.18% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 1      0.00%     65.18% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              2      0.00%     65.18% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     65.18% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     65.18% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     65.18% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     65.18% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     65.18% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     65.18% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc           759      0.00%     65.19% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     65.19% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            2      0.00%     65.19% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     65.19% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead            11614499     23.06%     88.25% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite            5918207     11.75%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total              50360925                       # Type of FU issued
system.cpu1.iq.rate                          0.729010                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                    1024601                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.020345                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads         152586143                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         74924785                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses     44270347                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads              12757                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes              7087                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses         5824                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses              51360226                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                   6678                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads          266055                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads      3973405                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses         7375                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation        12287                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores      1481060                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads      1850150                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked      1139659                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               3054413                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                2505400                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles                71046                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           56747555                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts           255776                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts             11085935                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts             7020391                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            408110                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                 28416                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                 3434                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents         12287                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect        384769                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect       125659                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              510428                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts             47569274                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts             10848117                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts          2791651                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                        51276                       # number of nop insts executed
system.cpu1.iew.exec_refs                    16673626                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                 5809146                       # Number of branches executed
system.cpu1.iew.exec_stores                   5825509                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.688599                       # Inst execution rate
system.cpu1.iew.wb_sent                      46311223                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                     44276171                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                 24275566                       # num instructions producing a value
system.cpu1.iew.wb_consumers                 44463888                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.640929                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.545961                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitCommittedInsts      38087596                       # The number of committed instructions
system.cpu1.commit.commitSquashedInsts       18562736                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls         519335                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           450588                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples     47661477                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.799127                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.835707                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     34693281     72.79%     72.79% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1      6099066     12.80%     85.59% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2      1834262      3.85%     89.44% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3       962147      2.02%     91.45% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4       825706      1.73%     93.19% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5       739217      1.55%     94.74% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6       588574      1.23%     95.97% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7       450580      0.95%     96.92% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8      1468644      3.08%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total     47661477                       # Number of insts commited each cycle
system.cpu1.commit.count                     38087596                       # Number of instructions committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                      12651861                       # Number of memory references committed
system.cpu1.commit.loads                      7112530                       # Number of loads committed
system.cpu1.commit.membars                     148745                       # Number of memory barriers committed
system.cpu1.commit.branches                   4804762                       # Number of branches committed
system.cpu1.commit.fp_insts                      5744                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                 34029989                       # Number of committed integer instructions.
system.cpu1.commit.function_calls              433336                       # Number of function calls committed.
system.cpu1.commit.bw_lim_events              1468644                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                   102084600                       # The number of ROB reads
system.cpu1.rob.rob_writes                  116474424                       # The number of ROB writes
system.cpu1.timesIdled                         450576                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                       18406597                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.committedInsts                   38063042                       # Number of Instructions Simulated
system.cpu1.committedInsts_total             38063042                       # Number of Instructions Simulated
system.cpu1.cpi                              1.814917                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.814917                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.550989                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.550989                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads               222881114                       # number of integer regfile reads
system.cpu1.int_regfile_writes               47167594                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                     4241                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                    1808                       # number of floating regfile writes
system.cpu1.misc_regfile_reads               77248425                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                323332                       # number of misc regfile writes
system.cpu1.icache.replacements                486491                       # number of replacements
system.cpu1.icache.tagsinuse               498.789046                       # Cycle average of tags in use
system.cpu1.icache.total_refs                 7677673                       # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs                487003                       # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs                 15.765145                       # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle           74237229000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::0           498.789046                       # Average occupied blocks per context
system.cpu1.icache.occ_percent::0            0.974197                       # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::0            7677673                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total        7677673                       # number of ReadReq hits
system.cpu1.icache.demand_hits::0             7677673                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::1                   0                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total         7677673                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::0            7677673                       # number of overall hits
system.cpu1.icache.overall_hits::1                  0                       # number of overall hits
system.cpu1.icache.overall_hits::total        7677673                       # number of overall hits
system.cpu1.icache.ReadReq_misses::0           528325                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       528325                       # number of ReadReq misses
system.cpu1.icache.demand_misses::0            528325                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::1                 0                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        528325                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::0           528325                       # number of overall misses
system.cpu1.icache.overall_misses::1                0                       # number of overall misses
system.cpu1.icache.overall_misses::total       528325                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency    7771273996                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency     7771273996                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency    7771273996                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::0        8205998                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total      8205998                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::0         8205998                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total      8205998                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::0        8205998                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total      8205998                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::0      0.064383                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::0       0.064383                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::0      0.064383                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::0 14709.267962                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::0 14709.267962                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::0 14709.267962                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs      1184497                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs              157                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs  7544.566879                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.writebacks                   18578                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_hits            41295                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits             41295                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits            41295                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses         487030                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses          487030                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses         487030                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency   5811540497                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency   5811540497                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency   5811540497                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency      2517500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency      2517500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::0     0.059350                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::0     0.059350                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::0     0.059350                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11932.612975                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency 11932.612975                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency 11932.612975                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.replacements                272380                       # number of replacements
system.cpu1.dcache.tagsinuse               444.916025                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                10412119                       # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs                272723                       # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs                 38.178368                       # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle           66749899000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::0           444.916025                       # Average occupied blocks per context
system.cpu1.dcache.occ_percent::0            0.868977                       # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::0            7081898                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        7081898                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::0           3139500                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       3139500                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::0        75302                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        75302                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::0         72598                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        72598                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::0            10221398                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total        10221398                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::0           10221398                       # number of overall hits
system.cpu1.dcache.overall_hits::1                  0                       # number of overall hits
system.cpu1.dcache.overall_hits::total       10221398                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::0           324241                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       324241                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::0         1274343                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total      1274343                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::0        12700                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        12700                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::0        11096                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        11096                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::0           1598584                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total       1598584                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::0          1598584                       # number of overall misses
system.cpu1.dcache.overall_misses::1                0                       # number of overall misses
system.cpu1.dcache.overall_misses::total      1598584                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency    5065302500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency  46249656862                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency    148116500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency     88362500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency    51314959362                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency   51314959362                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::0        7406139                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      7406139                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::0       4413843                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      4413843                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::0        88002                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        88002                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::0        83694                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        83694                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::0        11819982                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total     11819982                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::0       11819982                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total     11819982                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::0      0.043780                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::0     0.288715                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::0     0.144315                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::0     0.132578                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::0       0.135244                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::0      0.135244                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::0 15622.029601                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::0 36292.942216                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11662.716535                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::0  7963.455299                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::0 32100.258330                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::0 32100.258330                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs     13378551                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets      5449500                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs             3082                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets            157                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs  4340.866645                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets 34710.191083                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks                  223500                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits           134561                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits         1158019                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits          988                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits           1292580                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits          1292580                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses         189680                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses        116324                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses        11712                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses        11095                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses          306004                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses         306004                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency   2497244500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency   3447430551                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency     99180500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency     55002000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency   5944675051                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency   5944675051                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency   8455396000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency  41503639517                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency  49959035517                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::0     0.025611                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::0     0.026354                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0     0.133088                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0     0.132566                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::0     0.025889                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::0     0.025889                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13165.565690                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 29636.451214                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency  8468.280396                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency  4957.368184                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency 19426.788705                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency 19426.788705                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.iocache.replacements                         0                       # number of replacements
system.iocache.tagsinuse                            0                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
system.iocache.avg_refs                      no_value                       # Average number of references to valid blocks.
system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
system.iocache.overall_hits::0                      0                       # number of overall hits
system.iocache.overall_hits::1                      0                       # number of overall hits
system.iocache.overall_hits::total                  0                       # number of overall hits
system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
system.iocache.demand_misses::1                     0                       # number of demand (read+write) misses
system.iocache.demand_misses::total                 0                       # number of demand (read+write) misses
system.iocache.overall_misses::0                    0                       # number of overall misses
system.iocache.overall_misses::1                    0                       # number of overall misses
system.iocache.overall_misses::total                0                       # number of overall misses
system.iocache.demand_miss_latency                  0                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency                 0                       # number of overall miss cycles
system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
system.iocache.demand_accesses::1                   0                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total               0                       # number of demand (read+write) accesses
system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
system.iocache.overall_accesses::1                  0                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total              0                       # number of overall (read+write) accesses
system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
system.iocache.demand_miss_rate::1           no_value                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
system.iocache.overall_miss_rate::1          no_value                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
system.iocache.demand_avg_miss_latency::0     no_value                       # average overall miss latency
system.iocache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
system.iocache.overall_avg_miss_latency::0     no_value                       # average overall miss latency
system.iocache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks                           0                       # number of writebacks
system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
system.iocache.demand_mshr_misses                   0                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses                  0                       # number of overall MSHR misses
system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.iocache.demand_mshr_miss_latency             0                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_uncacheable_latency 1308164389827                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency 1308164389827                       # number of overall MSHR uncacheable cycles
system.iocache.demand_mshr_miss_rate::0      no_value                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::1      no_value                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::0     no_value                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
system.iocache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   55750                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                   41971                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------