path: root/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.503566                       # Number of seconds simulated
sim_ticks                                2503566110500                       # Number of ticks simulated
final_tick                               2503566110500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  76624                       # Simulator instruction rate (inst/s)
host_tick_rate                             2498140220                       # Simulator tick rate (ticks/s)
host_mem_usage                                 386188                       # Number of bytes of host memory used
host_seconds                                  1002.17                       # Real time elapsed on the host
sim_insts                                    76790007                       # Number of instructions simulated
system.nvmem.bytes_read                            64                       # Number of bytes read from this memory
system.nvmem.bytes_inst_read                       64                       # Number of instructions bytes read from this memory
system.nvmem.bytes_written                          0                       # Number of bytes written to this memory
system.nvmem.num_reads                              1                       # Number of read requests responded to by this memory
system.nvmem.num_writes                             0                       # Number of write requests responded to by this memory
system.nvmem.num_other                              0                       # Number of other requests responded to by this memory
system.nvmem.bw_read                               26                       # Total read bandwidth from this memory (bytes/s)
system.nvmem.bw_inst_read                          26                       # Instruction read bandwidth from this memory (bytes/s)
system.nvmem.bw_total                              26                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read                   130731152                       # Number of bytes read from this memory
system.physmem.bytes_inst_read                1101568                       # Number of instructions bytes read from this memory
system.physmem.bytes_written                  9585992                       # Number of bytes written to this memory
system.physmem.num_reads                     15117140                       # Number of read requests responded to by this memory
system.physmem.num_writes                      856673                       # Number of write requests responded to by this memory
system.physmem.num_other                            0                       # Number of other requests responded to by this memory
system.physmem.bw_read                       52217975                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read                    440000                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write                       3828935                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total                      56046910                       # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements                        119509                       # number of replacements
system.l2c.tagsinuse                     25929.897253                       # Cycle average of tags in use
system.l2c.total_refs                         1795434                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        150343                       # Sample count of references to valid blocks.
system.l2c.avg_refs                         11.942252                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::0                 11551.232252                       # Average occupied blocks per context
system.l2c.occ_blocks::1                 14378.665001                       # Average occupied blocks per context
system.l2c.occ_percent::0                    0.176258                       # Average percentage of cache occupancy
system.l2c.occ_percent::1                    0.219401                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::0                    1350292                       # number of ReadReq hits
system.l2c.ReadReq_hits::1                     153003                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1503295                       # number of ReadReq hits
system.l2c.Writeback_hits::0                   629881                       # number of Writeback hits
system.l2c.Writeback_hits::total               629881                       # number of Writeback hits
system.l2c.UpgradeReq_hits::0                      38                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                  38                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::0                    16                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                16                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::0                   105934                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               105934                       # number of ReadExReq hits
system.l2c.demand_hits::0                     1456226                       # number of demand (read+write) hits
system.l2c.demand_hits::1                      153003                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1609229                       # number of demand (read+write) hits
system.l2c.overall_hits::0                    1456226                       # number of overall hits
system.l2c.overall_hits::1                     153003                       # number of overall hits
system.l2c.overall_hits::total                1609229                       # number of overall hits
system.l2c.ReadReq_misses::0                    36080                       # number of ReadReq misses
system.l2c.ReadReq_misses::1                      144                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                36224                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::0                  3255                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              3255                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::0                   2                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total               2                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::0                 140433                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             140433                       # number of ReadExReq misses
system.l2c.demand_misses::0                    176513                       # number of demand (read+write) misses
system.l2c.demand_misses::1                       144                       # number of demand (read+write) misses
system.l2c.demand_misses::total                176657                       # number of demand (read+write) misses
system.l2c.overall_misses::0                   176513                       # number of overall misses
system.l2c.overall_misses::1                      144                       # number of overall misses
system.l2c.overall_misses::total               176657                       # number of overall misses
system.l2c.ReadReq_miss_latency            1894696500                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency            1006500                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency          7384268500                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency             9278965000                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency            9278965000                       # number of overall miss cycles
system.l2c.ReadReq_accesses::0                1386372                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::1                 153147                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1539519                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::0               629881                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           629881                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::0                3293                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            3293                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::0                18                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total            18                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::0               246367                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           246367                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::0                 1632739                       # number of demand (read+write) accesses
system.l2c.demand_accesses::1                  153147                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             1785886                       # number of demand (read+write) accesses
system.l2c.overall_accesses::0                1632739                       # number of overall (read+write) accesses
system.l2c.overall_accesses::1                 153147                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            1785886                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::0              0.026025                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::1              0.000940                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.026965                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::0           0.988460                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::0         0.111111                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::0            0.570015                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::0               0.108109                       # miss rate for demand accesses
system.l2c.demand_miss_rate::1               0.000940                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.109049                       # miss rate for demand accesses
system.l2c.overall_miss_rate::0              0.108109                       # miss rate for overall accesses
system.l2c.overall_miss_rate::1              0.000940                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.109049                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::0   52513.761086                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::1   13157614.583333                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 13210128.344420                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::0   309.216590                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::1          inf                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::0 52582.145934                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::1          inf                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::0    52568.167784                       # average overall miss latency
system.l2c.demand_avg_miss_latency::1    64437256.944444                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 64489825.112228                       # average overall miss latency
system.l2c.overall_avg_miss_latency::0   52568.167784                       # average overall miss latency
system.l2c.overall_avg_miss_latency::1   64437256.944444                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 64489825.112228                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks                          102655                       # number of writebacks
system.l2c.ReadReq_mshr_hits                       94                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits                        94                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits                       94                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses                  36130                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses                3255                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses                 2                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses               140433                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses                  176563                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses                 176563                       # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency       1449837500                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency     131527500                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency        80000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency     5640075000                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency        7089912500                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency       7089912500                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency 131769527500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency  32342636570                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency 164112164070                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::0         0.026061                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::1         0.235917                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.261978                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::0      0.988460                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::1           inf                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::0     0.111111                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::1          inf                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::0       0.570015                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::1            inf                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::0          0.108139                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::1          1.152899                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      1.261038                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::0         0.108139                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::1         1.152899                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     1.261038                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency 40128.355937                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency 40407.834101                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency        40000                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency 40162.034565                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency  40155.142923                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency 40155.142923                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                     52217329                       # DTB read hits
system.cpu.dtb.read_misses                      90306                       # DTB read misses
system.cpu.dtb.write_hits                    11974176                       # DTB write hits
system.cpu.dtb.write_misses                     25588                       # DTB write misses
system.cpu.dtb.flush_tlb                            2                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                     4349                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                      5563                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                    685                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                      2233                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                 52307635                       # DTB read accesses
system.cpu.dtb.write_accesses                11999764                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                          64191505                       # DTB hits
system.cpu.dtb.misses                          115894                       # DTB misses
system.cpu.dtb.accesses                      64307399                       # DTB accesses
system.cpu.itb.inst_hits                     14124795                       # ITB inst hits
system.cpu.itb.inst_misses                       9853                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            2                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                     2606                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                      7868                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                 14134648                       # ITB inst accesses
system.cpu.itb.hits                          14124795                       # DTB hits
system.cpu.itb.misses                            9853                       # DTB misses
system.cpu.itb.accesses                      14134648                       # DTB accesses
system.cpu.numCycles                        415912091                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.BPredUnit.lookups                 16206323                       # Number of BP lookups
system.cpu.BPredUnit.condPredicted           12554772                       # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect            1108177                       # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups              13916811                       # Number of BTB lookups
system.cpu.BPredUnit.BTBHits                 10226428                       # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS                  1423283                       # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect              227054                       # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles           32931583                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      104747250                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    16206323                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           11649711                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      24460631                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 7066944                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                     130925                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.BlockedCycles               92852979                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                 1378                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles        144764                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles       217141                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles          360                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  14116150                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes               1044696                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                    4826                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          155542524                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              0.838034                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             2.183637                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                131107701     84.29%     84.29% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  1736645      1.12%     85.41% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  2606210      1.68%     87.08% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  3650547      2.35%     89.43% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  2167045      1.39%     90.82% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  1435515      0.92%     91.75% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  2626627      1.69%     93.43% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                   854151      0.55%     93.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                  9358083      6.02%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            155542524                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.038966                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.251849                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 35137982                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              92713675                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  21969277                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               1093477                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                4628113                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved              2313056                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                177631                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              122001156                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                574106                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                4628113                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 37294552                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                36817406                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       49929047                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  20901153                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles               5972253                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              113826701                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                  4400                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                 914485                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               3979731                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents            42252                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           118358543                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups             523323093                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        523225639                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups             97454                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps              77492718                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 40865824                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts            1204637                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts        1098724                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  12304657                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             21982315                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            14168730                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1896802                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          2281380                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  102860211                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             1874616                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 126873316                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            252471                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        26973483                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     72956952                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         374923                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     155542524                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.815683                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.505358                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           108919716     70.03%     70.03% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            15115277      9.72%     79.74% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             7538109      4.85%     84.59% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             6517896      4.19%     88.78% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            12766129      8.21%     96.99% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             2735746      1.76%     98.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             1395145      0.90%     99.64% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              422031      0.27%     99.91% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              132475      0.09%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       155542524                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                   45891      0.52%      0.52% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      6      0.00%      0.52% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.52% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.52% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.52% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.52% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.52% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.52% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      0.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      0.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      0.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      0.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.52% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                8417784     94.58%     95.09% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                436630      4.91%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass            106530      0.08%      0.08% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              60069482     47.35%     47.43% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                96615      0.08%     47.51% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     47.51% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     47.51% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     47.51% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     47.51% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     47.51% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     47.51% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     47.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     47.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     47.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     47.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     47.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     47.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   8      0.00%     47.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     47.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     47.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     47.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               6      0.00%     47.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     47.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     47.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     47.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     47.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     47.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     47.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc           2251      0.00%     47.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            6      0.00%     47.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.51% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             53942685     42.52%     90.02% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            12655733      9.98%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              126873316                       # Type of FU issued
system.cpu.iq.rate                           0.305048                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     8900311                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.070151                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          418533128                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         131726191                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses     87292108                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads               24017                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes              13690                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses        10446                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              135654305                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                   12792                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads           614767                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      6301517                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        11128                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        32657                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      2389653                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads     34061869                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked       1153605                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                4628113                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                28345943                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                419499                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           104949442                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            473979                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              21982315                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             14168730                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts            1228031                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                  85187                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                  7556                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          32657                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         850397                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       257130                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              1107527                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             123429779                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              52914304                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           3443537                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                        214615                       # number of nop insts executed
system.cpu.iew.exec_refs                     65401525                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 11705842                       # Number of branches executed
system.cpu.iew.exec_stores                   12487221                       # Number of stores executed
system.cpu.iew.exec_rate                     0.296769                       # Inst execution rate
system.cpu.iew.wb_sent                      121771133                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                      87302554                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  47043389                       # num instructions producing a value
system.cpu.iew.wb_consumers                  86638668                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       0.209906                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.542984                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts       76940388                       # The number of committed instructions
system.cpu.commit.commitSquashedInsts        27793277                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         1499693                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            977065                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    150996763                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.509550                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.459324                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    122144480     80.89%     80.89% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     14839804      9.83%     90.72% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      4110999      2.72%     93.44% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      2181780      1.44%     94.89% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      1788910      1.18%     96.07% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1360879      0.90%     96.97% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      1262027      0.84%     97.81% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       662023      0.44%     98.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      2645861      1.75%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    150996763                       # Number of insts commited each cycle
system.cpu.commit.count                      76940388                       # Number of instructions committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       27459875                       # Number of memory references committed
system.cpu.commit.loads                      15680798                       # Number of loads committed
system.cpu.commit.membars                      413062                       # Number of memory barriers committed
system.cpu.commit.branches                    9891038                       # Number of branches committed
system.cpu.commit.fp_insts                      10212                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  68493475                       # Number of committed integer instructions.
system.cpu.commit.function_calls               995603                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               2645861                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    251328068                       # The number of ROB reads
system.cpu.rob.rob_writes                   214226863                       # The number of ROB writes
system.cpu.timesIdled                         1877486                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                       260369567                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   4591132146                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                    76790007                       # Number of Instructions Simulated
system.cpu.committedInsts_total              76790007                       # Number of Instructions Simulated
system.cpu.cpi                               5.416227                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         5.416227                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.184630                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.184630                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                559625786                       # number of integer regfile reads
system.cpu.int_regfile_writes                89694789                       # number of integer regfile writes
system.cpu.fp_regfile_reads                      8322                       # number of floating regfile reads
system.cpu.fp_regfile_writes                     2832                       # number of floating regfile writes
system.cpu.misc_regfile_reads               137256850                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 912282                       # number of misc regfile writes
system.cpu.icache.replacements                 991618                       # number of replacements
system.cpu.icache.tagsinuse                511.615309                       # Cycle average of tags in use
system.cpu.icache.total_refs                 13036767                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                 992130                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                  13.140180                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle             6445921000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0            511.615309                       # Average occupied blocks per context
system.cpu.icache.occ_percent::0             0.999249                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::0            13036767                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        13036767                       # number of ReadReq hits
system.cpu.icache.demand_hits::0             13036767                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::1                    0                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         13036767                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::0            13036767                       # number of overall hits
system.cpu.icache.overall_hits::1                   0                       # number of overall hits
system.cpu.icache.overall_hits::total        13036767                       # number of overall hits
system.cpu.icache.ReadReq_misses::0           1079261                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1079261                       # number of ReadReq misses
system.cpu.icache.demand_misses::0            1079261                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::1                  0                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1079261                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::0           1079261                       # number of overall misses
system.cpu.icache.overall_misses::1                 0                       # number of overall misses
system.cpu.icache.overall_misses::total       1079261                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency    15910722989                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency     15910722989                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency    15910722989                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::0        14116028                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     14116028                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::0         14116028                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::1                0                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     14116028                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::0        14116028                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     14116028                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::0       0.076456                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::0        0.076456                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::0       0.076456                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::0 14742.238429                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::0 14742.238429                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::0 14742.238429                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs      2475992                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               368                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs  6728.239130                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.writebacks                    57161                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits             87101                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits              87101                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits             87101                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses          992160                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses           992160                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses          992160                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency  11856676492                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency  11856676492                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency  11856676492                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency      6359500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency      6359500                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::0     0.070286                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::0     0.070286                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::0     0.070286                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11950.367372                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 11950.367372                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 11950.367372                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                 643915                       # number of replacements
system.cpu.dcache.tagsinuse                511.991681                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 22265831                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                 644427                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                  34.551363                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle               48663000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0            511.991681                       # Average occupied blocks per context
system.cpu.dcache.occ_percent::0             0.999984                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::0            14412375                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        14412375                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::0            7264610                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        7264610                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::0        299966                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       299966                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::0         285484                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       285484                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::0             21676985                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::1                    0                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         21676985                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::0            21676985                       # number of overall hits
system.cpu.dcache.overall_hits::1                   0                       # number of overall hits
system.cpu.dcache.overall_hits::total        21676985                       # number of overall hits
system.cpu.dcache.ReadReq_misses::0            724119                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        724119                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::0          2966647                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      2966647                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::0        13487                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        13487                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::0           18                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total           18                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::0            3690766                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::1                  0                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        3690766                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::0           3690766                       # number of overall misses
system.cpu.dcache.overall_misses::1                 0                       # number of overall misses
system.cpu.dcache.overall_misses::total       3690766                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency    10885048500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency  110351571736                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency    219032000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency       343000                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency    121236620236                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency   121236620236                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::0        15136494                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     15136494                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::0       10231257                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     10231257                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::0       313453                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       313453                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::0       285502                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       285502                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::0         25367751                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::1                0                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     25367751                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::0        25367751                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     25367751                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::0       0.047839                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::0      0.289959                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::0     0.043027                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::0     0.000063                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::0        0.145490                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::0       0.145490                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::0 15032.126626                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::0 37197.405602                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 16240.231334                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::0 19055.555556                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::0 32848.633654                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::0 32848.633654                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs     16787932                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets      7490000                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs              2999                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets             273                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs  5597.843281                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 27435.897436                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks                   572720                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits            338008                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits          2717083                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits         1442                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits            3055091                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits           3055091                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses          386111                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses         249564                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses        12045                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses           18                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses           635675                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses          635675                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency   5247540500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency   8926098932                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency    161654000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency       282500                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency  14173639432                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency  14173639432                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency 147158749000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency  42258178710                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 189416927710                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::0     0.025509                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::0     0.024392                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0     0.038427                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::0     0.000063                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::0     0.025058                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::0     0.025058                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13590.756285                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35766.772980                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 13420.838522                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 15694.444444                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 22296.990494                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 22296.990494                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.iocache.replacements                         0                       # number of replacements
system.iocache.tagsinuse                            0                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
system.iocache.avg_refs                      no_value                       # Average number of references to valid blocks.
system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
system.iocache.overall_hits::0                      0                       # number of overall hits
system.iocache.overall_hits::1                      0                       # number of overall hits
system.iocache.overall_hits::total                  0                       # number of overall hits
system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
system.iocache.demand_misses::1                     0                       # number of demand (read+write) misses
system.iocache.demand_misses::total                 0                       # number of demand (read+write) misses
system.iocache.overall_misses::0                    0                       # number of overall misses
system.iocache.overall_misses::1                    0                       # number of overall misses
system.iocache.overall_misses::total                0                       # number of overall misses
system.iocache.demand_miss_latency                  0                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency                 0                       # number of overall miss cycles
system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
system.iocache.demand_accesses::1                   0                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total               0                       # number of demand (read+write) accesses
system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
system.iocache.overall_accesses::1                  0                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total              0                       # number of overall (read+write) accesses
system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
system.iocache.demand_miss_rate::1           no_value                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
system.iocache.overall_miss_rate::1          no_value                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
system.iocache.demand_avg_miss_latency::0     no_value                       # average overall miss latency
system.iocache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
system.iocache.overall_avg_miss_latency::0     no_value                       # average overall miss latency
system.iocache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks                           0                       # number of writebacks
system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
system.iocache.demand_mshr_misses                   0                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses                  0                       # number of overall MSHR misses
system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.iocache.demand_mshr_miss_latency             0                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_uncacheable_latency 1307898920918                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency 1307898920918                       # number of overall MSHR uncacheable cycles
system.iocache.demand_mshr_miss_rate::0      no_value                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::1      no_value                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::0     no_value                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
system.iocache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                    87985                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------