path: root/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.080738                       # Number of seconds simulated
sim_ticks                                 80737865500                       # Number of ticks simulated
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  39525                       # Simulator instruction rate (inst/s)
host_tick_rate                               61513284                       # Simulator tick rate (ticks/s)
host_mem_usage                                 368852                       # Number of bytes of host memory used
host_seconds                                  1312.53                       # Real time elapsed on the host
sim_insts                                    51877265                       # Number of instructions simulated
system.l2c.replacements                         94990                       # number of replacements
system.l2c.tagsinuse                     38163.791653                       # Cycle average of tags in use
system.l2c.total_refs                         1058289                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        127415                       # Sample count of references to valid blocks.
system.l2c.avg_refs                          8.305843                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::0                  6719.704145                       # Average occupied blocks per context
system.l2c.occ_blocks::1                 31444.087508                       # Average occupied blocks per context
system.l2c.occ_percent::0                    0.102535                       # Average percentage of cache occupancy
system.l2c.occ_percent::1                    0.479799                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::0                     746044                       # number of ReadReq hits
system.l2c.ReadReq_hits::1                     122406                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                 868450                       # number of ReadReq hits
system.l2c.Writeback_hits::0                   435356                       # number of Writeback hits
system.l2c.Writeback_hits::total               435356                       # number of Writeback hits
system.l2c.UpgradeReq_hits::0                      23                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                  23                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::0                    60912                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                60912                       # number of ReadExReq hits
system.l2c.demand_hits::0                      806956                       # number of demand (read+write) hits
system.l2c.demand_hits::1                      122406                       # number of demand (read+write) hits
system.l2c.demand_hits::total                  929362                       # number of demand (read+write) hits
system.l2c.overall_hits::0                     806956                       # number of overall hits
system.l2c.overall_hits::1                     122406                       # number of overall hits
system.l2c.overall_hits::total                 929362                       # number of overall hits
system.l2c.ReadReq_misses::0                    21087                       # number of ReadReq misses
system.l2c.ReadReq_misses::1                      100                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                21187                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::0                  1678                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              1678                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::0                 107779                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             107779                       # number of ReadExReq misses
system.l2c.demand_misses::0                    128866                       # number of demand (read+write) misses
system.l2c.demand_misses::1                       100                       # number of demand (read+write) misses
system.l2c.demand_misses::total                128966                       # number of demand (read+write) misses
system.l2c.overall_misses::0                   128866                       # number of overall misses
system.l2c.overall_misses::1                      100                       # number of overall misses
system.l2c.overall_misses::total               128966                       # number of overall misses
system.l2c.ReadReq_miss_latency            1107503500                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency             728500                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency          5653158500                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency             6760662000                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency            6760662000                       # number of overall miss cycles
system.l2c.ReadReq_accesses::0                 767131                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::1                 122506                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total             889637                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::0               435356                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           435356                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::0                1701                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            1701                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::0               168691                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           168691                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::0                  935822                       # number of demand (read+write) accesses
system.l2c.demand_accesses::1                  122506                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             1058328                       # number of demand (read+write) accesses
system.l2c.overall_accesses::0                 935822                       # number of overall (read+write) accesses
system.l2c.overall_accesses::1                 122506                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            1058328                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::0              0.027488                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::1              0.000816                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.028304                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::0           0.986479                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::0            0.638914                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::0               0.137704                       # miss rate for demand accesses
system.l2c.demand_miss_rate::1               0.000816                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.138520                       # miss rate for demand accesses
system.l2c.overall_miss_rate::0              0.137704                       # miss rate for overall accesses
system.l2c.overall_miss_rate::1              0.000816                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.138520                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::0   52520.676246                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::1       11075035                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 11127555.676246                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::0   434.147795                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::1          inf                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::0 52451.391273                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::1          inf                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::0    52462.728726                       # average overall miss latency
system.l2c.demand_avg_miss_latency::1        67606620                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 67659082.728726                       # average overall miss latency
system.l2c.overall_avg_miss_latency::0   52462.728726                       # average overall miss latency
system.l2c.overall_avg_miss_latency::1       67606620                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 67659082.728726                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks                           87808                       # number of writebacks
system.l2c.ReadReq_mshr_hits                       58                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits                        58                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits                       58                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses                  21129                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses                1678                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses               107779                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses                  128908                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses                 128908                       # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency        846277000                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency      67121500                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency     4312433500                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency        5158710500                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency       5158710500                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency  28946618500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency    748700947                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency  29695319447                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::0         0.027543                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::1         0.172473                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.200016                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::0      0.986479                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::1           inf                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::0       0.638914                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::1            inf                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::0          0.137748                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::1          1.052259                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      1.190007                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::0         0.137748                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::1         1.052259                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     1.190007                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency 40052.865730                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency 40000.893921                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency 40011.815845                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency  40018.544233                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency 40018.544233                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                     28173336                       # DTB read hits
system.cpu.dtb.read_misses                      72357                       # DTB read misses
system.cpu.dtb.write_hits                     7689868                       # DTB write hits
system.cpu.dtb.write_misses                     13508                       # DTB write misses
system.cpu.dtb.flush_tlb                            2                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid               33678                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                      40                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                     2893                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                      4130                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                   1099                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                       947                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                 28245693                       # DTB read accesses
system.cpu.dtb.write_accesses                 7703376                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                          35863204                       # DTB hits
system.cpu.dtb.misses                           85865                       # DTB misses
system.cpu.dtb.accesses                      35949069                       # DTB accesses
system.cpu.itb.inst_hits                      7353914                       # ITB inst hits
system.cpu.itb.inst_misses                       7640                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            2                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid               33678                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                      40                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                     1653                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                      4537                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                  7361554                       # ITB inst accesses
system.cpu.itb.hits                           7353914                       # DTB hits
system.cpu.itb.misses                            7640                       # DTB misses
system.cpu.itb.accesses                       7361554                       # DTB accesses
system.cpu.numCycles                        161475732                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.BPredUnit.lookups                 13591178                       # Number of BP lookups
system.cpu.BPredUnit.condPredicted           11457422                       # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect             648522                       # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups              12128132                       # Number of BTB lookups
system.cpu.BPredUnit.BTBHits                  9358408                       # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS                   895734                       # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect              148980                       # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles           16857885                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                       67476093                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    13591178                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           10254142                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      17027869                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 4121673                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                      92046                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.BlockedCycles               55386928                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                18221                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles         89652                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles          207                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                   7348854                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                337711                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                    4423                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples           92501381                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              0.899926                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             2.157722                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 75492420     81.61%     81.61% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  1419002      1.53%     83.15% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  1862378      2.01%     85.16% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  1400658      1.51%     86.67% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  4890175      5.29%     91.96% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                   936188      1.01%     92.97% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                   816395      0.88%     93.86% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                   714688      0.77%     94.63% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                  4969477      5.37%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total             92501381                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.084169                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.417871                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 18958860                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              54056295                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  15357354                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               1172463                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                2956409                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved              1326398                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                 73852                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts               80374481                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                240410                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                2956409                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 20599609                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                33473612                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       16533693                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  13871976                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles               5066082                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts               77012867                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                458143                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                 143852                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               2656312                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents               95                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands            79085152                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups             335784610                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        335718375                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups             66235                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps              51887619                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 27197532                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts             847968                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         665693                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  14024127                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             13553811                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores             9176054                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads               336                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores              727                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                   69112553                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             4041097                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                  82084831                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            240436                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        20591364                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     41997995                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved        1078252                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples      92501381                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.887390                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.470670                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            58092899     62.80%     62.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            14059432     15.20%     78.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             6650253      7.19%     85.19% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             4536722      4.90%     90.10% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             6374682      6.89%     96.99% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             1627400      1.76%     98.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6              756790      0.82%     99.56% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              287365      0.31%     99.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              115838      0.13%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total        92501381                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                   27880      0.57%      0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      2      0.00%      0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                4534214     92.60%     93.17% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                334260      6.83%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass           2393223      2.92%      2.92% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              42161035     51.36%     54.28% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                71794      0.09%     54.37% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     54.37% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     54.37% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     54.37% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     54.37% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     54.37% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     54.37% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     54.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     54.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     54.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     54.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     54.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     54.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                  20      0.00%     54.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     54.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     54.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     54.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc              16      0.00%     54.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     54.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     54.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     54.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     54.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     54.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     54.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc            886      0.00%     54.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     54.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc           16      0.00%     54.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     54.37% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             29245049     35.63%     89.99% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite             8212792     10.01%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total               82084831                       # Type of FU issued
system.cpu.iq.rate                           0.508342                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     4896356                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.059650                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          261876505                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes          94085418                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses     62678710                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads               16660                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes               9610                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses         6498                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses               84579214                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                    8750                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads           426405                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      4374283                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        13506                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation       404883                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      2098607                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads     17025185                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked          9489                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                2956409                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                21375540                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                254618                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts            73323080                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            354650                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              13553811                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts              9176054                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts            4009524                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                  13227                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 41701                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents         404883                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         534659                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       173860                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               708519                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts              80709483                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              28679216                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           1375348                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                        169430                       # number of nop insts executed
system.cpu.iew.exec_refs                     36683219                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 10550397                       # Number of branches executed
system.cpu.iew.exec_stores                    8004003                       # Number of stores executed
system.cpu.iew.exec_rate                     0.499824                       # Inst execution rate
system.cpu.iew.wb_sent                       80077641                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                      62685208                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  33194716                       # num instructions producing a value
system.cpu.iew.wb_consumers                  59585530                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       0.388202                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.557094                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts       52000495                       # The number of committed instructions
system.cpu.commit.commitSquashedInsts        19085580                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         2962845                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            622953                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples     89545000                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.580719                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.463730                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     69882025     78.04%     78.04% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1      9239055     10.32%     88.36% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      2669928      2.98%     91.34% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      1384390      1.55%     92.89% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      3444558      3.85%     96.73% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5       816353      0.91%     97.65% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       554324      0.62%     98.26% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       352463      0.39%     98.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      1201904      1.34%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total     89545000                       # Number of insts commited each cycle
system.cpu.commit.count                      52000495                       # Number of instructions committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       16256975                       # Number of memory references committed
system.cpu.commit.loads                       9179528                       # Number of loads committed
system.cpu.commit.membars                           3                       # Number of memory barriers committed
system.cpu.commit.branches                    8429180                       # Number of branches committed
system.cpu.commit.fp_insts                       6017                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  42424017                       # Number of committed integer instructions.
system.cpu.commit.function_calls               530190                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               1201904                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    158488078                       # The number of ROB reads
system.cpu.rob.rob_writes                   145173632                       # The number of ROB writes
system.cpu.timesIdled                         1073836                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                        68974351                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                    51877265                       # Number of Instructions Simulated
system.cpu.committedInsts_total              51877265                       # Number of Instructions Simulated
system.cpu.cpi                               3.112649                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         3.112649                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.321270                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.321270                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                356080640                       # number of integer regfile reads
system.cpu.int_regfile_writes                64700984                       # number of integer regfile writes
system.cpu.fp_regfile_reads                      5701                       # number of floating regfile reads
system.cpu.fp_regfile_writes                     1958                       # number of floating regfile writes
system.cpu.misc_regfile_reads                88406544                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 512521                       # number of misc regfile writes
system.cpu.icache.replacements                 512688                       # number of replacements
system.cpu.icache.tagsinuse                496.953841                       # Cycle average of tags in use
system.cpu.icache.total_refs                  6780185                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                 513200                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                  13.211584                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle             5987250000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0            496.953841                       # Average occupied blocks per context
system.cpu.icache.occ_percent::0             0.970613                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::0             6780185                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total         6780185                       # number of ReadReq hits
system.cpu.icache.demand_hits::0              6780185                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::1                    0                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total          6780185                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::0             6780185                       # number of overall hits
system.cpu.icache.overall_hits::1                   0                       # number of overall hits
system.cpu.icache.overall_hits::total         6780185                       # number of overall hits
system.cpu.icache.ReadReq_misses::0            568554                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        568554                       # number of ReadReq misses
system.cpu.icache.demand_misses::0             568554                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::1                  0                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         568554                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::0            568554                       # number of overall misses
system.cpu.icache.overall_misses::1                 0                       # number of overall misses
system.cpu.icache.overall_misses::total        568554                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency     8372040495                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency      8372040495                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency     8372040495                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::0         7348739                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total      7348739                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::0          7348739                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::1                0                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total      7348739                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::0         7348739                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total      7348739                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::0       0.077368                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::0        0.077368                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::0       0.077368                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::0 14725.145712                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::0 14725.145712                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::0 14725.145712                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs      1711497                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               225                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs  7606.653333                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.writebacks                    43018                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits             55350                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits              55350                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits             55350                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses          513204                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses           513204                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses          513204                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency   6207353497                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency   6207353497                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency   6207353497                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency      5831500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency      5831500                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::0     0.069836                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::0     0.069836                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::0     0.069836                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 12095.294458                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 12095.294458                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 12095.294458                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                 424603                       # number of replacements
system.cpu.dcache.tagsinuse                511.742300                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 14088098                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                 425115                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                  33.139499                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle               48622000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0            511.742300                       # Average occupied blocks per context
system.cpu.dcache.occ_percent::0             0.999497                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::0             9259812                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total         9259812                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::0            4617727                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        4617727                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::0        103769                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       103769                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::0         104969                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       104969                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::0             13877539                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::1                    0                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         13877539                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::0            13877539                       # number of overall hits
system.cpu.dcache.overall_hits::1                   0                       # number of overall hits
system.cpu.dcache.overall_hits::total        13877539                       # number of overall hits
system.cpu.dcache.ReadReq_misses::0            532190                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        532190                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::0          2045201                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      2045201                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::0         6628                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total         6628                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::0            2577391                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::1                  0                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        2577391                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::0           2577391                       # number of overall misses
system.cpu.dcache.overall_misses::1                 0                       # number of overall misses
system.cpu.dcache.overall_misses::total       2577391                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency     7843477000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency   81654653268                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency     99384000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency     89498130268                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency    89498130268                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::0         9792002                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total      9792002                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::0        6662928                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      6662928                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::0       110397                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       110397                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::0       104969                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       104969                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::0         16454930                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::1                0                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     16454930                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::0        16454930                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     16454930                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::0       0.054349                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::0      0.306952                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::0     0.060038                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::0        0.156633                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::0       0.156633                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::0 14738.114207                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::0 39925.001635                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14994.568497                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::0 34724.312403                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::0 34724.312403                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs      9952489                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets       866000                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs              1361                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets              31                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs  7312.629684                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 27935.483871                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks                   392338                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits            281320                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits          1874850                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits         1033                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits            2156170                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits           2156170                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses          250870                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses         170351                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses         5595                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses           421221                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses          421221                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency   3354520500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency   6559724489                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency     66444000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency   9914244989                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency   9914244989                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency  38199664000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency    946836164                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency  39146500164                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::0     0.025620                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::0     0.025567                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0     0.050681                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::0     0.025598                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::0     0.025598                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13371.549009                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 38507.108787                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11875.603217                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 23536.920023                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 23536.920023                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.iocache.replacements                         0                       # number of replacements
system.iocache.tagsinuse                            0                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
system.iocache.avg_refs                      no_value                       # Average number of references to valid blocks.
system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
system.iocache.overall_hits::0                      0                       # number of overall hits
system.iocache.overall_hits::1                      0                       # number of overall hits
system.iocache.overall_hits::total                  0                       # number of overall hits
system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
system.iocache.demand_misses::1                     0                       # number of demand (read+write) misses
system.iocache.demand_misses::total                 0                       # number of demand (read+write) misses
system.iocache.overall_misses::0                    0                       # number of overall misses
system.iocache.overall_misses::1                    0                       # number of overall misses
system.iocache.overall_misses::total                0                       # number of overall misses
system.iocache.demand_miss_latency                  0                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency                 0                       # number of overall miss cycles
system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
system.iocache.demand_accesses::1                   0                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total               0                       # number of demand (read+write) accesses
system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
system.iocache.overall_accesses::1                  0                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total              0                       # number of overall (read+write) accesses
system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
system.iocache.demand_miss_rate::1           no_value                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
system.iocache.overall_miss_rate::1          no_value                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
system.iocache.demand_avg_miss_latency::0     no_value                       # average overall miss latency
system.iocache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
system.iocache.overall_avg_miss_latency::0     no_value                       # average overall miss latency
system.iocache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks                           0                       # number of writebacks
system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
system.iocache.demand_mshr_misses                   0                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses                  0                       # number of overall MSHR misses
system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.iocache.demand_mshr_miss_latency             0                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.iocache.demand_mshr_miss_rate::0      no_value                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::1      no_value                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::0     no_value                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
system.iocache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------