path: root/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.080755                       # Number of seconds simulated
sim_ticks                                 80755049500                       # Number of ticks simulated
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  42177                       # Simulator instruction rate (inst/s)
host_tick_rate                               65656485                       # Simulator tick rate (ticks/s)
host_mem_usage                                 388872                       # Number of bytes of host memory used
host_seconds                                  1229.96                       # Real time elapsed on the host
sim_insts                                    51876527                       # Number of instructions simulated
system.l2c.replacements                         94951                       # number of replacements
system.l2c.tagsinuse                     38190.664860                       # Cycle average of tags in use
system.l2c.total_refs                         1060547                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        127388                       # Sample count of references to valid blocks.
system.l2c.avg_refs                          8.325329                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::0                  6775.267374                       # Average occupied blocks per context
system.l2c.occ_blocks::1                 31415.397486                       # Average occupied blocks per context
system.l2c.occ_percent::0                    0.103382                       # Average percentage of cache occupancy
system.l2c.occ_percent::1                    0.479361                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::0                     745613                       # number of ReadReq hits
system.l2c.ReadReq_hits::1                     120260                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                 865873                       # number of ReadReq hits
system.l2c.Writeback_hits::0                   435187                       # number of Writeback hits
system.l2c.Writeback_hits::total               435187                       # number of Writeback hits
system.l2c.UpgradeReq_hits::0                      26                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                  26                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::0                     1                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                 1                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::0                    60895                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                60895                       # number of ReadExReq hits
system.l2c.demand_hits::0                      806508                       # number of demand (read+write) hits
system.l2c.demand_hits::1                      120260                       # number of demand (read+write) hits
system.l2c.demand_hits::total                  926768                       # number of demand (read+write) hits
system.l2c.overall_hits::0                     806508                       # number of overall hits
system.l2c.overall_hits::1                     120260                       # number of overall hits
system.l2c.overall_hits::total                 926768                       # number of overall hits
system.l2c.ReadReq_misses::0                    21201                       # number of ReadReq misses
system.l2c.ReadReq_misses::1                      103                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                21304                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::0                  1679                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              1679                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::0                 107626                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             107626                       # number of ReadExReq misses
system.l2c.demand_misses::0                    128827                       # number of demand (read+write) misses
system.l2c.demand_misses::1                       103                       # number of demand (read+write) misses
system.l2c.demand_misses::total                128930                       # number of demand (read+write) misses
system.l2c.overall_misses::0                   128827                       # number of overall misses
system.l2c.overall_misses::1                      103                       # number of overall misses
system.l2c.overall_misses::total               128930                       # number of overall misses
system.l2c.ReadReq_miss_latency            1113607000                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency             728500                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency          5645255000                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency             6758862000                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency            6758862000                       # number of overall miss cycles
system.l2c.ReadReq_accesses::0                 766814                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::1                 120363                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total             887177                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::0               435187                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           435187                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::0                1705                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            1705                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::0                 1                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total             1                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::0               168521                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           168521                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::0                  935335                       # number of demand (read+write) accesses
system.l2c.demand_accesses::1                  120363                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             1055698                       # number of demand (read+write) accesses
system.l2c.overall_accesses::0                 935335                       # number of overall (read+write) accesses
system.l2c.overall_accesses::1                 120363                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            1055698                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::0              0.027648                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::1              0.000856                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.028504                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::0           0.984751                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::0            0.638650                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::0               0.137734                       # miss rate for demand accesses
system.l2c.demand_miss_rate::1               0.000856                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.138589                       # miss rate for demand accesses
system.l2c.overall_miss_rate::0              0.137734                       # miss rate for overall accesses
system.l2c.overall_miss_rate::1              0.000856                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.138589                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::0   52526.154427                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::1   10811718.446602                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 10864244.601029                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::0   433.889220                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::1          inf                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::0 52452.520766                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::1          inf                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::0    52464.638624                       # average overall miss latency
system.l2c.demand_avg_miss_latency::1    65620019.417476                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 65672484.056100                       # average overall miss latency
system.l2c.overall_avg_miss_latency::0   52464.638624                       # average overall miss latency
system.l2c.overall_avg_miss_latency::1   65620019.417476                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 65672484.056100                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks                           87785                       # number of writebacks
system.l2c.ReadReq_mshr_hits                       53                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits                        53                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits                       53                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses                  21251                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses                1679                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses               107626                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses                  128877                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses                 128877                       # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency        851149000                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency      67161500                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency     4306288000                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency        5157437000                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency       5157437000                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency  28946617000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency    748511947                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency  29695128947                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::0         0.027713                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::1         0.176558                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.204271                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::0      0.984751                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::1           inf                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::0       0.638650                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::1            inf                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::0          0.137787                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::1          1.070736                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      1.208523                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::0         0.137787                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::1         1.070736                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     1.208523                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency 40052.185779                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency 40000.893389                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency 40011.595711                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency  40018.288756                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency 40018.288756                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                     28171950                       # DTB read hits
system.cpu.dtb.read_misses                      70965                       # DTB read misses
system.cpu.dtb.write_hits                     7689357                       # DTB write hits
system.cpu.dtb.write_misses                     13471                       # DTB write misses
system.cpu.dtb.flush_tlb                            2                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid               33678                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                      40                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                     2907                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                      3957                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                   1100                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                       937                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                 28242915                       # DTB read accesses
system.cpu.dtb.write_accesses                 7702828                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                          35861307                       # DTB hits
system.cpu.dtb.misses                           84436                       # DTB misses
system.cpu.dtb.accesses                      35945743                       # DTB accesses
system.cpu.itb.inst_hits                      7359425                       # ITB inst hits
system.cpu.itb.inst_misses                       7724                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            2                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid               33678                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                      40                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                     1636                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                      4501                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                  7367149                       # ITB inst accesses
system.cpu.itb.hits                           7359425                       # DTB hits
system.cpu.itb.misses                            7724                       # DTB misses
system.cpu.itb.accesses                       7367149                       # DTB accesses
system.cpu.numCycles                        161510100                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.BPredUnit.lookups                 13592134                       # Number of BP lookups
system.cpu.BPredUnit.condPredicted           11458436                       # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect             647586                       # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups              12137714                       # Number of BTB lookups
system.cpu.BPredUnit.BTBHits                  9358977                       # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS                   895744                       # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect              148599                       # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles           17070311                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                       67524465                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    13592134                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           10254721                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      17041944                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 4127061                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                      97740                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.BlockedCycles               55394199                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                13347                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles         87578                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles          326                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                   7354402                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                335871                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                    4520                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples           92740913                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              0.898020                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             2.156020                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 75718007     81.64%     81.64% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  1434363      1.55%     83.19% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  1859616      2.01%     85.20% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  1401287      1.51%     86.71% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  4885783      5.27%     91.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                   931795      1.00%     92.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                   822935      0.89%     93.87% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                   710992      0.77%     94.63% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                  4976135      5.37%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total             92740913                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.084157                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.418082                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 19170041                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              54062693                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  15371067                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               1173897                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                2963215                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved              1326018                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                 73901                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts               80423771                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                240700                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                2963215                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 20809926                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                33458987                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       16554506                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  13888577                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles               5065702                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts               77066395                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                458305                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                 144597                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               2655814                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents               87                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands            79138164                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups             336039029                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        335972600                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups             66429                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps              51886671                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 27251492                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts             849161                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         666808                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  14017436                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             13569563                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores             9186562                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads               338                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores              772                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                   69168297                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             4042083                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                  82065002                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            260128                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        20656291                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     42322701                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved        1079276                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples      92740913                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.884885                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.468016                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            58298864     62.86%     62.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            14093921     15.20%     78.06% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             6658255      7.18%     85.24% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             4544945      4.90%     90.14% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             6367225      6.87%     97.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             1625042      1.75%     98.76% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6              756452      0.82%     99.57% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              282758      0.30%     99.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              113451      0.12%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total        92740913                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                   27418      0.56%      0.56% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      1      0.00%      0.56% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.56% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.56% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.56% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.56% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.56% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.56% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      0.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      0.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      0.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      0.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.56% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                4528688     92.69%     93.25% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                329972      6.75%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass           2393223      2.92%      2.92% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              42145979     51.36%     54.27% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                71705      0.09%     54.36% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     54.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     54.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     54.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     54.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     54.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     54.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     54.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     54.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     54.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     54.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    1      0.00%     54.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     54.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                  15      0.00%     54.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     54.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     54.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  1      0.00%     54.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc              13      0.00%     54.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     54.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     54.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     54.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     54.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     54.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     54.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc            889      0.00%     54.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     54.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc           14      0.00%     54.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     54.36% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             29241712     35.63%     89.99% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite             8211450     10.01%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total               82065002                       # Type of FU issued
system.cpu.iq.rate                           0.508111                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     4886079                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.059539                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          262084445                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes          94207895                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses     62666625                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads               16580                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes               9518                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses         6446                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses               84549185                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                    8673                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads           425184                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      4390114                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        12978                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation       404267                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      2109214                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads     17025483                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked          9484                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                2963215                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                21359658                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                253804                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts            73379873                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            352437                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              13569563                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts              9186562                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts            4009981                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                  13852                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 40391                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents         404267                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         533633                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       173680                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               707313                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts              80695154                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              28677244                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           1369848                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                        169493                       # number of nop insts executed
system.cpu.iew.exec_refs                     36680386                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 10545987                       # Number of branches executed
system.cpu.iew.exec_stores                    8003142                       # Number of stores executed
system.cpu.iew.exec_rate                     0.499629                       # Inst execution rate
system.cpu.iew.wb_sent                       80067231                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                      62673071                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  33197180                       # num instructions producing a value
system.cpu.iew.wb_consumers                  59582018                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       0.388044                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.557168                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts       51999757                       # The number of committed instructions
system.cpu.commit.commitSquashedInsts        19143621                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         2962807                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            621959                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples     89777726                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.579206                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.461343                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     70089240     78.07%     78.07% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1      9267844     10.32%     88.39% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      2668316      2.97%     91.36% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      1388119      1.55%     92.91% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      3443383      3.84%     96.75% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5       819971      0.91%     97.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       549038      0.61%     98.27% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       351211      0.39%     98.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      1200604      1.34%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total     89777726                       # Number of insts commited each cycle
system.cpu.commit.count                      51999757                       # Number of instructions committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       16256797                       # Number of memory references committed
system.cpu.commit.loads                       9179449                       # Number of loads committed
system.cpu.commit.membars                           3                       # Number of memory barriers committed
system.cpu.commit.branches                    8428992                       # Number of branches committed
system.cpu.commit.fp_insts                       6017                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  42423491                       # Number of committed integer instructions.
system.cpu.commit.function_calls               530190                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               1200604                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    158779407                       # The number of ROB reads
system.cpu.rob.rob_writes                   145294275                       # The number of ROB writes
system.cpu.timesIdled                         1055860                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                        68769187                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                    51876527                       # Number of Instructions Simulated
system.cpu.committedInsts_total              51876527                       # Number of Instructions Simulated
system.cpu.cpi                               3.113356                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         3.113356                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.321197                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.321197                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                356027200                       # number of integer regfile reads
system.cpu.int_regfile_writes                64685711                       # number of integer regfile writes
system.cpu.fp_regfile_reads                      5606                       # number of floating regfile reads
system.cpu.fp_regfile_writes                     1941                       # number of floating regfile writes
system.cpu.misc_regfile_reads                88439585                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 512449                       # number of misc regfile writes
system.cpu.icache.replacements                 512265                       # number of replacements
system.cpu.icache.tagsinuse                496.983905                       # Cycle average of tags in use
system.cpu.icache.total_refs                  6786376                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                 512777                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                  13.234556                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle             5988099000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0            496.983905                       # Average occupied blocks per context
system.cpu.icache.occ_percent::0             0.970672                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::0             6786376                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total         6786376                       # number of ReadReq hits
system.cpu.icache.demand_hits::0              6786376                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::1                    0                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total          6786376                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::0             6786376                       # number of overall hits
system.cpu.icache.overall_hits::1                   0                       # number of overall hits
system.cpu.icache.overall_hits::total         6786376                       # number of overall hits
system.cpu.icache.ReadReq_misses::0            567912                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        567912                       # number of ReadReq misses
system.cpu.icache.demand_misses::0             567912                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::1                  0                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         567912                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::0            567912                       # number of overall misses
system.cpu.icache.overall_misses::1                 0                       # number of overall misses
system.cpu.icache.overall_misses::total        567912                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency     8362680490                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency      8362680490                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency     8362680490                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::0         7354288                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total      7354288                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::0          7354288                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::1                0                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total      7354288                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::0         7354288                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total      7354288                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::0       0.077222                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::0        0.077222                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::0       0.077222                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::0 14725.310418                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::0 14725.310418                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::0 14725.310418                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs      1857992                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               226                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs  8221.203540                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.writebacks                    42978                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits             55127                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits              55127                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits             55127                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses          512785                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses           512785                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses          512785                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency   6200973492                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency   6200973492                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency   6200973492                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency      5831500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency      5831500                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::0     0.069726                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::0     0.069726                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::0     0.069726                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 12092.735731                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 12092.735731                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 12092.735731                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                 424546                       # number of replacements
system.cpu.dcache.tagsinuse                511.742424                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 14088944                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                 425058                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                  33.145933                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle               48611000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0            511.742424                       # Average occupied blocks per context
system.cpu.dcache.occ_percent::0             0.999497                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::0             9259661                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total         9259661                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::0            4618854                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        4618854                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::0        103684                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       103684                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::0         104934                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       104934                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::0             13878515                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::1                    0                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         13878515                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::0            13878515                       # number of overall hits
system.cpu.dcache.overall_hits::1                   0                       # number of overall hits
system.cpu.dcache.overall_hits::total        13878515                       # number of overall hits
system.cpu.dcache.ReadReq_misses::0            532064                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        532064                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::0          2044074                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      2044074                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::0         6626                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total         6626                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::0            1                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            1                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::0            2576138                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::1                  0                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        2576138                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::0           2576138                       # number of overall misses
system.cpu.dcache.overall_misses::1                 0                       # number of overall misses
system.cpu.dcache.overall_misses::total       2576138                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency     7831574000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency   81582591763                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency     99296500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency        14500                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency     89414165763                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency    89414165763                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::0         9791725                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total      9791725                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::0        6662928                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      6662928                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::0       110310                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       110310                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::0       104935                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       104935                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::0         16454653                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::1                0                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     16454653                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::0        16454653                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     16454653                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::0       0.054338                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::0      0.306783                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::0     0.060067                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::0     0.000010                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::0        0.156560                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::0       0.156560                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::0 14719.233025                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::0 39911.760417                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14985.888922                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::0        14500                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::0 34708.608686                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::0 34708.608686                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs      9862991                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets       855500                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs              1356                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets              31                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs  7273.592183                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 27596.774194                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks                   392209                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits            281075                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits          1873891                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits         1035                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits            2154966                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits           2154966                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses          250989                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses         170183                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses         5591                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses            1                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses           421172                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses          421172                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency   3359805000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency   6551180491                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency     66352500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency        11000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency   9910985491                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency   9910985491                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency  38199653000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency    946485168                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency  39146138168                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::0     0.025633                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::0     0.025542                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0     0.050684                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::0     0.000010                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::0     0.025596                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::0     0.025596                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13386.263940                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 38494.917183                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11867.733858                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency        11000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 23531.919242                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 23531.919242                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.iocache.replacements                         0                       # number of replacements
system.iocache.tagsinuse                            0                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
system.iocache.avg_refs                      no_value                       # Average number of references to valid blocks.
system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
system.iocache.overall_hits::0                      0                       # number of overall hits
system.iocache.overall_hits::1                      0                       # number of overall hits
system.iocache.overall_hits::total                  0                       # number of overall hits
system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
system.iocache.demand_misses::1                     0                       # number of demand (read+write) misses
system.iocache.demand_misses::total                 0                       # number of demand (read+write) misses
system.iocache.overall_misses::0                    0                       # number of overall misses
system.iocache.overall_misses::1                    0                       # number of overall misses
system.iocache.overall_misses::total                0                       # number of overall misses
system.iocache.demand_miss_latency                  0                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency                 0                       # number of overall miss cycles
system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
system.iocache.demand_accesses::1                   0                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total               0                       # number of demand (read+write) accesses
system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
system.iocache.overall_accesses::1                  0                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total              0                       # number of overall (read+write) accesses
system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
system.iocache.demand_miss_rate::1           no_value                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
system.iocache.overall_miss_rate::1          no_value                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
system.iocache.demand_avg_miss_latency::0     no_value                       # average overall miss latency
system.iocache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
system.iocache.overall_avg_miss_latency::0     no_value                       # average overall miss latency
system.iocache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks                           0                       # number of writebacks
system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
system.iocache.demand_mshr_misses                   0                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses                  0                       # number of overall MSHR misses
system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.iocache.demand_mshr_miss_latency             0                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.iocache.demand_mshr_miss_rate::0      no_value                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::1      no_value                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::0     no_value                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
system.iocache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------