path: root/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  5.145287                       # Number of seconds simulated
sim_ticks                                5145286546500                       # Number of ticks simulated
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 252508                       # Simulator instruction rate (inst/s)
host_tick_rate                             1546872935                       # Simulator tick rate (ticks/s)
host_mem_usage                                 390244                       # Number of bytes of host memory used
host_seconds                                  3326.25                       # Real time elapsed on the host
sim_insts                                   839904894                       # Number of instructions simulated
system.l2c.replacements                        171120                       # number of replacements
system.l2c.tagsinuse                     38411.926866                       # Cycle average of tags in use
system.l2c.total_refs                         3818646                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        206013                       # Sample count of references to valid blocks.
system.l2c.avg_refs                         18.535947                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::0                 11983.527500                       # Average occupied blocks per context
system.l2c.occ_blocks::1                 26428.399366                       # Average occupied blocks per context
system.l2c.occ_percent::0                    0.182854                       # Average percentage of cache occupancy
system.l2c.occ_percent::1                    0.403265                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::0                    2330328                       # number of ReadReq hits
system.l2c.ReadReq_hits::1                     145914                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                2476242                       # number of ReadReq hits
system.l2c.Writeback_hits::0                  1599020                       # number of Writeback hits
system.l2c.Writeback_hits::total              1599020                       # number of Writeback hits
system.l2c.UpgradeReq_hits::0                     343                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 343                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::0                   150210                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               150210                       # number of ReadExReq hits
system.l2c.demand_hits::0                     2480538                       # number of demand (read+write) hits
system.l2c.demand_hits::1                      145914                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2626452                       # number of demand (read+write) hits
system.l2c.overall_hits::0                    2480538                       # number of overall hits
system.l2c.overall_hits::1                     145914                       # number of overall hits
system.l2c.overall_hits::total                2626452                       # number of overall hits
system.l2c.ReadReq_misses::0                    68080                       # number of ReadReq misses
system.l2c.ReadReq_misses::1                       84                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                68164                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::0                  3905                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              3905                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::0                 142426                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             142426                       # number of ReadExReq misses
system.l2c.demand_misses::0                    210506                       # number of demand (read+write) misses
system.l2c.demand_misses::1                        84                       # number of demand (read+write) misses
system.l2c.demand_misses::total                210590                       # number of demand (read+write) misses
system.l2c.overall_misses::0                   210506                       # number of overall misses
system.l2c.overall_misses::1                       84                       # number of overall misses
system.l2c.overall_misses::total               210590                       # number of overall misses
system.l2c.ReadReq_miss_latency            3574844000                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency           37228000                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency          7453066500                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency            11027910500                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency           11027910500                       # number of overall miss cycles
system.l2c.ReadReq_accesses::0                2398408                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::1                 145998                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2544406                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::0              1599020                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total          1599020                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::0                4248                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            4248                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::0               292636                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           292636                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::0                 2691044                       # number of demand (read+write) accesses
system.l2c.demand_accesses::1                  145998                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2837042                       # number of demand (read+write) accesses
system.l2c.overall_accesses::0                2691044                       # number of overall (read+write) accesses
system.l2c.overall_accesses::1                 145998                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2837042                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::0              0.028385                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::1              0.000575                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.028961                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::0           0.919256                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::0            0.486700                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::0               0.078225                       # miss rate for demand accesses
system.l2c.demand_miss_rate::1               0.000575                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.078800                       # miss rate for demand accesses
system.l2c.overall_miss_rate::0              0.078225                       # miss rate for overall accesses
system.l2c.overall_miss_rate::1              0.000575                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.078800                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::0   52509.459459                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::1   42557666.666667                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 42610176.126126                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::0  9533.418694                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::1          inf                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::0 52329.395616                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::1          inf                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::0    52387.630281                       # average overall miss latency
system.l2c.demand_avg_miss_latency::1    131284648.809524                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 131337036.439805                       # average overall miss latency
system.l2c.overall_avg_miss_latency::0   52387.630281                       # average overall miss latency
system.l2c.overall_avg_miss_latency::1   131284648.809524                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 131337036.439805                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks                          142550                       # number of writebacks
system.l2c.ReadReq_mshr_hits                        2                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits                         2                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits                        2                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses                  68162                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses                3905                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses               142426                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses                  210588                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses                 210588                       # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency       2743592500                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency     156565000                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency     5717024500                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency        8460617000                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency       8460617000                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency  61532546500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency   1222452000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency  62754998500                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::0         0.028420                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::1         0.466869                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.495289                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::0      0.919256                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::1           inf                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::0       0.486700                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::1            inf                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::0          0.078255                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::1          1.442403                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      1.520658                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::0         0.078255                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::1         1.442403                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     1.520658                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency 40251.056307                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency 40093.469910                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency 40140.314971                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency  40176.159135                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency 40176.159135                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.iocache.replacements                     47572                       # number of replacements
system.iocache.tagsinuse                     0.146650                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                     47588                       # Sample count of references to valid blocks.
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.warmup_cycle              4994510051000                       # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::1                 0.146650                       # Average occupied blocks per context
system.iocache.occ_percent::1                0.009166                       # Average percentage of cache occupancy
system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
system.iocache.overall_hits::0                      0                       # number of overall hits
system.iocache.overall_hits::1                      0                       # number of overall hits
system.iocache.overall_hits::total                  0                       # number of overall hits
system.iocache.ReadReq_misses::1                  907                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              907                       # number of ReadReq misses
system.iocache.WriteReq_misses::1               46720                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
system.iocache.demand_misses::1                 47627                       # number of demand (read+write) misses
system.iocache.demand_misses::total             47627                       # number of demand (read+write) misses
system.iocache.overall_misses::0                    0                       # number of overall misses
system.iocache.overall_misses::1                47627                       # number of overall misses
system.iocache.overall_misses::total            47627                       # number of overall misses
system.iocache.ReadReq_miss_latency         113785932                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency       6369912160                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency         6483698092                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency        6483698092                       # number of overall miss cycles
system.iocache.ReadReq_accesses::1                907                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            907                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::1             46720                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
system.iocache.demand_accesses::1               47627                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           47627                       # number of demand (read+write) accesses
system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
system.iocache.overall_accesses::1              47627                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          47627                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::1                 1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::1                1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
system.iocache.demand_miss_rate::1                  1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
system.iocache.overall_miss_rate::1                 1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::1 125453.067255                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::0          inf                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::1 136342.297945                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::0          inf                       # average overall miss latency
system.iocache.demand_avg_miss_latency::1 136134.925399                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.iocache.overall_avg_miss_latency::0          inf                       # average overall miss latency
system.iocache.overall_avg_miss_latency::1 136134.925399                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs      68669502                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                11260                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs  6098.534813                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks                       46667                       # number of writebacks
system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
system.iocache.ReadReq_mshr_misses                907                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses             46720                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses               47627                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses              47627                       # number of overall MSHR misses
system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.iocache.ReadReq_mshr_miss_latency     66598982                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency   3940155856                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency    4006754838                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency   4006754838                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::1            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::0          inf                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::1            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::0           inf                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::1             1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::1            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency 73427.764057                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency 84335.527740                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency 84127.802255                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency 84127.802255                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs           32                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
system.cpu.numCycles                        449021643                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.BPredUnit.lookups                 91138491                       # Number of BP lookups
system.cpu.BPredUnit.condPredicted           91138491                       # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect            1248082                       # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups              89857544                       # Number of BTB lookups
system.cpu.BPredUnit.BTBHits                 83686998                       # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles           28288670                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      450771327                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    91138491                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           83686998                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     171087914                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 6045536                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                     191873                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.BlockedCycles               82674920                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                36392                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles         54951                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles          281                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                   9822160                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                542562                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                    4016                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          287044907                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              3.085924                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.403637                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                116472661     40.58%     40.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  1490084      0.52%     41.10% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 72800190     25.36%     66.46% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  1427390      0.50%     66.95% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  1806479      0.63%     67.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  3992507      1.39%     68.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  1571582      0.55%     69.52% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  2063795      0.72%     70.24% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 85420219     29.76%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            287044907                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.202971                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.003897                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 33370892                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              79040686                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 165533455                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               4389968                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                4709906                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts              881886507                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                   578                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                4709906                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 37547254                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                52554502                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       10077381                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 165462513                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              16693351                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              877383155                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                 14371                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents               11668719                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               2142745                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands           879650717                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            1723132927                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       1723132383                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups               544                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             843287047                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 36363663                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts             486686                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         487762                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  43318784                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             19666821                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            10717044                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1121000                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          1013044                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  870450598                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded              900193                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 866206507                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            178001                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        30597956                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     44655599                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         144106                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     287044907                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         3.017669                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.373774                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            82633676     28.79%     28.79% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            22379993      7.80%     36.58% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            14042555      4.89%     41.48% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             9676323      3.37%     44.85% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            79535811     27.71%     72.56% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             5032653      1.75%     74.31% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            72954170     25.42%     99.72% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              636902      0.22%     99.95% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              152824      0.05%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       287044907                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  195893      8.77%      8.77% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%      8.77% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      8.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      8.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      8.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      8.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      8.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      8.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      8.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      8.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      8.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      8.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      8.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      8.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      8.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      8.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      8.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      8.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      8.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      8.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      8.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      8.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      8.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      8.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      8.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      8.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      8.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      8.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      8.77% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                1841396     82.43%     91.19% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                196729      8.81%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass            302784      0.03%      0.03% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             830728417     95.90%     95.94% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                    0      0.00%     95.94% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     95.94% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     95.94% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     95.94% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     95.94% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     95.94% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     95.94% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     95.94% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     95.94% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     95.94% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     95.94% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     95.94% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     95.94% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     95.94% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     95.94% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     95.94% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     95.94% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     95.94% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     95.94% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     95.94% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     95.94% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     95.94% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     95.94% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     95.94% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     95.94% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     95.94% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     95.94% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     95.94% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             25630184      2.96%     98.90% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite             9545122      1.10%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              866206507                       # Type of FU issued
system.cpu.iq.rate                           1.929097                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     2234018                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.002579                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         2022023513                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         901959019                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    855369267                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 203                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                252                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           52                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              868137651                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                      90                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          1362479                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      4321864                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        17926                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        11344                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      2286443                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads      7817280                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked        160300                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                4709906                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                33528904                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               6021560                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           871350791                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            302780                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              19666821                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             10717077                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts             894230                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                5567968                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 26441                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          11344                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         900317                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       526461                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              1426778                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             864071451                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              25139822                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           2135055                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                     34444060                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 86704764                       # Number of branches executed
system.cpu.iew.exec_stores                    9304238                       # Number of stores executed
system.cpu.iew.exec_rate                     1.924343                       # Inst execution rate
system.cpu.iew.wb_sent                      863434483                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     855369319                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 671433691                       # num instructions producing a value
system.cpu.iew.wb_consumers                1171953644                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.904962                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.572918                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts      839904894                       # The number of committed instructions
system.cpu.commit.commitSquashedInsts        31338704                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls          756085                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           1254700                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    282350978                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     2.974684                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.863709                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    102836465     36.42%     36.42% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     12523164      4.44%     40.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      4697520      1.66%     42.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     76975529     27.26%     69.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      4042949      1.43%     71.21% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1857352      0.66%     71.87% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      1067382      0.38%     72.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7     71607681     25.36%     97.61% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      6742936      2.39%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    282350978                       # Number of insts commited each cycle
system.cpu.commit.count                     839904894                       # Number of instructions committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       23775588                       # Number of memory references committed
system.cpu.commit.loads                      15344954                       # Number of loads committed
system.cpu.commit.membars                        3541                       # Number of memory barriers committed
system.cpu.commit.branches                   85526796                       # Number of branches committed
system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 768518485                       # Number of committed integer instructions.
system.cpu.commit.function_calls                    0                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               6742936                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   1146769000                       # The number of ROB reads
system.cpu.rob.rob_writes                  1747209492                       # The number of ROB writes
system.cpu.timesIdled                         3079387                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                       161976736                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   839904894                       # Number of Instructions Simulated
system.cpu.committedInsts_total             839904894                       # Number of Instructions Simulated
system.cpu.cpi                               0.534610                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.534610                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.870522                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.870522                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               1407118516                       # number of integer regfile reads
system.cpu.int_regfile_writes               857404874                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        52                       # number of floating regfile reads
system.cpu.misc_regfile_reads               282285829                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 410057                       # number of misc regfile writes
system.cpu.icache.replacements                1028866                       # number of replacements
system.cpu.icache.tagsinuse                510.467349                       # Cycle average of tags in use
system.cpu.icache.total_refs                  8724446                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                1029378                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                   8.475454                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle            54553290000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0            510.467349                       # Average occupied blocks per context
system.cpu.icache.occ_percent::0             0.997007                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::0             8724446                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total         8724446                       # number of ReadReq hits
system.cpu.icache.demand_hits::0              8724446                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::1                    0                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total          8724446                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::0             8724446                       # number of overall hits
system.cpu.icache.overall_hits::1                   0                       # number of overall hits
system.cpu.icache.overall_hits::total         8724446                       # number of overall hits
system.cpu.icache.ReadReq_misses::0           1097711                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1097711                       # number of ReadReq misses
system.cpu.icache.demand_misses::0            1097711                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::1                  0                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1097711                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::0           1097711                       # number of overall misses
system.cpu.icache.overall_misses::1                 0                       # number of overall misses
system.cpu.icache.overall_misses::total       1097711                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency    16447038991                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency     16447038991                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency    16447038991                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::0         9822157                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total      9822157                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::0          9822157                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::1                0                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total      9822157                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::0         9822157                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total      9822157                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::0       0.111759                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::0        0.111759                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::0       0.111759                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::0 14983.031956                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::0 14983.031956                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::0 14983.031956                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs      2545992                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               258                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs  9868.186047                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.writebacks                     1562                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits             65787                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits              65787                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits             65787                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses         1031924                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses          1031924                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses         1031924                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency  12476028992                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency  12476028992                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency  12476028992                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::0     0.105061                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::0     0.105061                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::0     0.105061                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 12090.065734                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 12090.065734                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 12090.065734                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.itb_walker_cache.replacements        14158                       # number of replacements
system.cpu.itb_walker_cache.tagsinuse        6.014381                       # Cycle average of tags in use
system.cpu.itb_walker_cache.total_refs          26217                       # Total number of references to valid blocks.
system.cpu.itb_walker_cache.sampled_refs        14168                       # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.avg_refs         1.850438                       # Average number of references to valid blocks.
system.cpu.itb_walker_cache.warmup_cycle 5108050090000                       # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.occ_blocks::1     6.014381                       # Average occupied blocks per context
system.cpu.itb_walker_cache.occ_percent::1     0.375899                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.ReadReq_hits::1        26573                       # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total        26573                       # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::1            3                       # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total            3                       # number of WriteReq hits
system.cpu.itb_walker_cache.demand_hits::0            0                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::1        26576                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total        26576                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::0            0                       # number of overall hits
system.cpu.itb_walker_cache.overall_hits::1        26576                       # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total        26576                       # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::1        15025                       # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total        15025                       # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::0            0                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::1        15025                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total        15025                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::0            0                       # number of overall misses
system.cpu.itb_walker_cache.overall_misses::1        15025                       # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total        15025                       # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency    189764500                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency    189764500                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency    189764500                       # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::1        41598                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total        41598                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::1            3                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total            3                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.demand_accesses::0            0                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::1        41601                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total        41601                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::0            0                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::1        41601                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total        41601                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::1     0.361195                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::0     no_value                       # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::1     0.361169                       # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::0     no_value                       # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::1     0.361169                       # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::1 12629.916805                       # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::0          inf                       # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::1 12629.916805                       # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::0          inf                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::1 12629.916805                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.itb_walker_cache.writebacks           2705                       # number of writebacks
system.cpu.itb_walker_cache.demand_mshr_hits            0                       # number of demand (read+write) MSHR hits
system.cpu.itb_walker_cache.overall_mshr_hits            0                       # number of overall MSHR hits
system.cpu.itb_walker_cache.ReadReq_mshr_misses        15025                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses        15025                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses        15025                       # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency    144320000                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency    144320000                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency    144320000                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::1     0.361195                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::0          inf                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::1     0.361169                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::1     0.361169                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency  9605.324459                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency  9605.324459                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency  9605.324459                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.itb_walker_cache.mshr_cap_events            0                       # number of times MSHR cap was activated
system.cpu.itb_walker_cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.replacements       144708                       # number of replacements
system.cpu.dtb_walker_cache.tagsinuse       13.855241                       # Cycle average of tags in use
system.cpu.dtb_walker_cache.total_refs         146935                       # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.sampled_refs       144723                       # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.avg_refs         1.015284                       # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.warmup_cycle 5098934458000                       # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.occ_blocks::1    13.855241                       # Average occupied blocks per context
system.cpu.dtb_walker_cache.occ_percent::1     0.865953                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.ReadReq_hits::1       147187                       # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total       147187                       # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::0            0                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::1       147187                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total       147187                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::0            0                       # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::1       147187                       # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total       147187                       # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::1       145638                       # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total       145638                       # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::0            0                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::1       145638                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total       145638                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::0            0                       # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::1       145638                       # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total       145638                       # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency   2011660500                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency   2011660500                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency   2011660500                       # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::1       292825                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total       292825                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::0            0                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::1       292825                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total       292825                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::0            0                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::1       292825                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total       292825                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::1     0.497355                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::0     no_value                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::1     0.497355                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::0     no_value                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::1     0.497355                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::1 13812.744613                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::0          inf                       # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 13812.744613                       # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::0          inf                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 13812.744613                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.dtb_walker_cache.writebacks          46772                       # number of writebacks
system.cpu.dtb_walker_cache.demand_mshr_hits            0                       # number of demand (read+write) MSHR hits
system.cpu.dtb_walker_cache.overall_mshr_hits            0                       # number of overall MSHR hits
system.cpu.dtb_walker_cache.ReadReq_mshr_misses       145638                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses       145638                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses       145638                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency   1570780000                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency   1570780000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency   1570780000                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::1     0.497355                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::0          inf                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1     0.497355                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1     0.497355                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency 10785.509276                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency 10785.509276                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency 10785.509276                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.dtb_walker_cache.mshr_cap_events            0                       # number of times MSHR cap was activated
system.cpu.dtb_walker_cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                1661747                       # number of replacements
system.cpu.dcache.tagsinuse                511.998367                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 17960054                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                1662259                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                  10.804606                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle               13135000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0            511.998367                       # Average occupied blocks per context
system.cpu.dcache.occ_percent::0             0.999997                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::0            11390626                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        11390626                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::0            6547450                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        6547450                       # number of WriteReq hits
system.cpu.dcache.demand_hits::0             17938076                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::1                    0                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         17938076                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::0            17938076                       # number of overall hits
system.cpu.dcache.overall_hits::1                   0                       # number of overall hits
system.cpu.dcache.overall_hits::total        17938076                       # number of overall hits
system.cpu.dcache.ReadReq_misses::0           2490346                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       2490346                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::0          1873884                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1873884                       # number of WriteReq misses
system.cpu.dcache.demand_misses::0            4364230                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::1                  0                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        4364230                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::0           4364230                       # number of overall misses
system.cpu.dcache.overall_misses::1                 0                       # number of overall misses
system.cpu.dcache.overall_misses::total       4364230                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency    37598789500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency   63471421475                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency    101070210975                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency   101070210975                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::0        13880972                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     13880972                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::0        8421334                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      8421334                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::0         22302306                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::1                0                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     22302306                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::0        22302306                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     22302306                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::0       0.179407                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::0      0.222516                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::0        0.195685                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::0       0.195685                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::0 15097.817532                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::0 33871.585154                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::0 23158.772790                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::0 23158.772790                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs   1083244649                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets      6672500                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs             73213                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets             391                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 14795.796498                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 17065.217391                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks                  1547981                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits           1120147                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits          1577106                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits            2697253                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits           2697253                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses         1370199                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses         296778                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses          1666977                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses         1666977                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency  18186929000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency   9757421649                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency  27944350649                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency  27944350649                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency  86947016500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency   1386048000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency  88333064500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::0     0.098711                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::0     0.035241                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::0     0.074745                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::0     0.074745                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13273.202652                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32877.846906                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 16763.489028                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 16763.489028                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------