path: root/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  5.151639                       # Number of seconds simulated
sim_ticks                                5151638875500                       # Number of ticks simulated
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 136272                       # Simulator instruction rate (inst/s)
host_tick_rate                              835912815                       # Simulator tick rate (ticks/s)
host_mem_usage                                 404376                       # Number of bytes of host memory used
host_seconds                                  6162.89                       # Real time elapsed on the host
sim_insts                                   839831731                       # Number of instructions simulated
system.l2c.replacements                        168782                       # number of replacements
system.l2c.tagsinuse                     38205.196893                       # Cycle average of tags in use
system.l2c.total_refs                         3762867                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        202558                       # Sample count of references to valid blocks.
system.l2c.avg_refs                         18.576739                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::0                 11735.089031                       # Average occupied blocks per context
system.l2c.occ_blocks::1                 26470.107863                       # Average occupied blocks per context
system.l2c.occ_percent::0                    0.179063                       # Average percentage of cache occupancy
system.l2c.occ_percent::1                    0.403902                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::0                    2331067                       # number of ReadReq hits
system.l2c.ReadReq_hits::1                     125887                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                2456954                       # number of ReadReq hits
system.l2c.Writeback_hits::0                  1588356                       # number of Writeback hits
system.l2c.Writeback_hits::total              1588356                       # number of Writeback hits
system.l2c.UpgradeReq_hits::0                     357                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 357                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::0                   150454                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               150454                       # number of ReadExReq hits
system.l2c.demand_hits::0                     2481521                       # number of demand (read+write) hits
system.l2c.demand_hits::1                      125887                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2607408                       # number of demand (read+write) hits
system.l2c.overall_hits::0                    2481521                       # number of overall hits
system.l2c.overall_hits::1                     125887                       # number of overall hits
system.l2c.overall_hits::total                2607408                       # number of overall hits
system.l2c.ReadReq_misses::0                    64696                       # number of ReadReq misses
system.l2c.ReadReq_misses::1                       91                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                64787                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::0                  3960                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              3960                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::0                 142190                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             142190                       # number of ReadExReq misses
system.l2c.demand_misses::0                    206886                       # number of demand (read+write) misses
system.l2c.demand_misses::1                        91                       # number of demand (read+write) misses
system.l2c.demand_misses::total                206977                       # number of demand (read+write) misses
system.l2c.overall_misses::0                   206886                       # number of overall misses
system.l2c.overall_misses::1                       91                       # number of overall misses
system.l2c.overall_misses::total               206977                       # number of overall misses
system.l2c.ReadReq_miss_latency            3398610000                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency           37586500                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency          7439728500                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency            10838338500                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency           10838338500                       # number of overall miss cycles
system.l2c.ReadReq_accesses::0                2395763                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::1                 125978                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2521741                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::0              1588356                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total          1588356                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::0                4317                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            4317                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::0               292644                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           292644                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::0                 2688407                       # number of demand (read+write) accesses
system.l2c.demand_accesses::1                  125978                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2814385                       # number of demand (read+write) accesses
system.l2c.overall_accesses::0                2688407                       # number of overall (read+write) accesses
system.l2c.overall_accesses::1                 125978                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2814385                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::0              0.027004                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::1              0.000722                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.027727                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::0           0.917304                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::0            0.485880                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::0               0.076955                       # miss rate for demand accesses
system.l2c.demand_miss_rate::1               0.000722                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.077677                       # miss rate for demand accesses
system.l2c.overall_miss_rate::0              0.076955                       # miss rate for overall accesses
system.l2c.overall_miss_rate::1              0.000722                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.077677                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::0   52531.995796                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::1   37347362.637363                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 37399894.633158                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::0  9491.540404                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::1          inf                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::0 52322.445320                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::1          inf                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::0    52387.974537                       # average overall miss latency
system.l2c.demand_avg_miss_latency::1    119102620.879121                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 119155008.853658                       # average overall miss latency
system.l2c.overall_avg_miss_latency::0   52387.974537                       # average overall miss latency
system.l2c.overall_avg_miss_latency::1   119102620.879121                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 119155008.853658                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks                          142964                       # number of writebacks
system.l2c.ReadReq_mshr_hits                        2                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits                         2                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits                        2                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses                  64785                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses                3960                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses               142190                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses                  206975                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses                 206975                       # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency       2608555500                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency     158748000                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency     5705556000                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency        8314111500                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency       8314111500                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency  61533015500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency   1222291500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency  62755307000                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::0         0.027041                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::1         0.514256                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.541298                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::0      0.917304                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::1           inf                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::0       0.485880                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::1            inf                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::0          0.076988                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::1          1.642946                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      1.719934                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::0         0.076988                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::1         1.642946                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     1.719934                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency 40264.806668                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency 40087.878788                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency 40126.281736                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency  40169.641261                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency 40169.641261                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.iocache.replacements                     47575                       # number of replacements
system.iocache.tagsinuse                     0.165993                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                     47591                       # Sample count of references to valid blocks.
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.warmup_cycle              4994554828000                       # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::1                 0.165993                       # Average occupied blocks per context
system.iocache.occ_percent::1                0.010375                       # Average percentage of cache occupancy
system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
system.iocache.overall_hits::0                      0                       # number of overall hits
system.iocache.overall_hits::1                      0                       # number of overall hits
system.iocache.overall_hits::total                  0                       # number of overall hits
system.iocache.ReadReq_misses::1                  909                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              909                       # number of ReadReq misses
system.iocache.WriteReq_misses::1               46720                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
system.iocache.demand_misses::1                 47629                       # number of demand (read+write) misses
system.iocache.demand_misses::total             47629                       # number of demand (read+write) misses
system.iocache.overall_misses::0                    0                       # number of overall misses
system.iocache.overall_misses::1                47629                       # number of overall misses
system.iocache.overall_misses::total            47629                       # number of overall misses
system.iocache.ReadReq_miss_latency         113908932                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency       6372665160                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency         6486574092                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency        6486574092                       # number of overall miss cycles
system.iocache.ReadReq_accesses::1                909                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            909                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::1             46720                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
system.iocache.demand_accesses::1               47629                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           47629                       # number of demand (read+write) accesses
system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
system.iocache.overall_accesses::1              47629                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          47629                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::1                 1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::1                1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
system.iocache.demand_miss_rate::1                  1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
system.iocache.overall_miss_rate::1                 1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::1 125312.356436                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::0          inf                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::1 136401.223459                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::0          inf                       # average overall miss latency
system.iocache.demand_avg_miss_latency::1 136189.592307                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.iocache.overall_avg_miss_latency::0          inf                       # average overall miss latency
system.iocache.overall_avg_miss_latency::1 136189.592307                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs      68832452                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                11274                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs  6105.415292                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks                       46668                       # number of writebacks
system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
system.iocache.ReadReq_mshr_misses                909                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses             46720                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses               47629                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses              47629                       # number of overall MSHR misses
system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.iocache.ReadReq_mshr_miss_latency     66617982                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency   3942909802                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency    4009527784                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency   4009527784                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::1            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::0          inf                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::1            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::0           inf                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::1             1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::1            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency 73287.108911                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency 84394.473502                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency 84182.489324                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency 84182.489324                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs           32                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
system.cpu.numCycles                        449440116                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.BPredUnit.lookups                 91251942                       # Number of BP lookups
system.cpu.BPredUnit.condPredicted           91251942                       # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect            1248755                       # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups              89986362                       # Number of BTB lookups
system.cpu.BPredUnit.BTBHits                 83883414                       # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles           28443020                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      451559426                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    91251942                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           83883414                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     171343402                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 6212938                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                     155361                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.BlockedCycles               82525667                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                36777                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles         48486                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles          319                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                   9929678                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                556225                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                    4240                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          287412747                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              3.086350                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.403158                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                116615067     40.57%     40.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  1502902      0.52%     41.10% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 72824785     25.34%     66.44% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  1334009      0.46%     66.90% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  1960992      0.68%     67.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  4008264      1.39%     68.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  1565099      0.54%     69.52% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  2187101      0.76%     70.28% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 85414528     29.72%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            287412747                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.203035                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.004715                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 33501642                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              78913894                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 165819274                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               4318222                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                4859715                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts              883193903                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                   620                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                4859715                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 37708099                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                52423571                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       10078562                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 165633752                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              16709048                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              878518097                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                 13834                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents               11653087                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               2148761                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents                8                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           880915046                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            1725729327                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       1725728311                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups              1016                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             843223982                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 37691057                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts             489641                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         492542                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  43070507                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             19803638                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            10755992                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           3194647                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          3198862                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  871443389                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded              900411                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 866326988                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            165756                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        31682293                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     47289832                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         148825                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     287412747                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         3.014226                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.369116                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            82109167     28.57%     28.57% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            23029898      8.01%     36.58% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            14429245      5.02%     41.60% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             9845202      3.43%     45.03% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            79549613     27.68%     72.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             4871174      1.69%     74.40% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            72852960     25.35%     99.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              572992      0.20%     99.95% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              152496      0.05%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       287412747                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  198235      9.39%      9.39% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%      9.39% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      9.39% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      9.39% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      9.39% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      9.39% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      9.39% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      9.39% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      9.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      9.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      9.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      9.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      9.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      9.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      9.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      9.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      9.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      9.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      9.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      9.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      9.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      9.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      9.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      9.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      9.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      9.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      9.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      9.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.39% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                1790050     84.77%     94.16% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                123321      5.84%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass            300321      0.03%      0.03% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             831068974     95.93%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                    0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             25494883      2.94%     98.91% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite             9462810      1.09%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              866326988                       # Type of FU issued
system.cpu.iq.rate                           1.927569                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     2111606                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.002437                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         2022483969                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         904056296                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    855552025                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 163                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                498                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           60                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              868138190                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                      83                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          1311048                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      4470522                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        13972                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        31558                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      2334229                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads      7818225                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked        154758                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                4859715                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                33597470                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               6022609                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           872343800                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            300494                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              19803638                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             10756022                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts             899609                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                5535817                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 26257                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          31558                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         897955                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       529978                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              1427933                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             864227296                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              25025491                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           2099691                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                     34264216                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 86728541                       # Number of branches executed
system.cpu.iew.exec_stores                    9238725                       # Number of stores executed
system.cpu.iew.exec_rate                     1.922898                       # Inst execution rate
system.cpu.iew.wb_sent                      863623792                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     855552085                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 671682498                       # num instructions producing a value
system.cpu.iew.wb_consumers                1172193952                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.903595                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.573013                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts      839831731                       # The number of committed instructions
system.cpu.commit.commitSquashedInsts        32406647                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls          751584                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           1254294                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    282568841                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     2.972131                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.859839                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    102495617     36.27%     36.27% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     13009464      4.60%     40.88% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      4878881      1.73%     42.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     76962899     27.24%     69.84% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      4022439      1.42%     71.26% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1857740      0.66%     71.92% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      1158664      0.41%     72.33% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7     71619728     25.35%     97.68% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      6563409      2.32%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    282568841                       # Number of insts commited each cycle
system.cpu.commit.count                     839831731                       # Number of instructions committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       23754906                       # Number of memory references committed
system.cpu.commit.loads                      15333113                       # Number of loads committed
system.cpu.commit.membars                         801                       # Number of memory barriers committed
system.cpu.commit.branches                   85519800                       # Number of branches committed
system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 768449243                       # Number of committed integer instructions.
system.cpu.commit.function_calls                    0                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               6563409                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   1148162427                       # The number of ROB reads
system.cpu.rob.rob_writes                  1749350545                       # The number of ROB writes
system.cpu.timesIdled                         3069835                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                       162027369                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   839831731                       # Number of Instructions Simulated
system.cpu.committedInsts_total             839831731                       # Number of Instructions Simulated
system.cpu.cpi                               0.535155                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.535155                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.868618                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.868618                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               1406651660                       # number of integer regfile reads
system.cpu.int_regfile_writes               857603051                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        60                       # number of floating regfile reads
system.cpu.misc_regfile_reads               282221875                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 407507                       # number of misc regfile writes
system.cpu.icache.replacements                1029232                       # number of replacements
system.cpu.icache.tagsinuse                510.471706                       # Cycle average of tags in use
system.cpu.icache.total_refs                  8833811                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                1029744                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                   8.578648                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle            54597932000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0            510.471706                       # Average occupied blocks per context
system.cpu.icache.occ_percent::0             0.997015                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::0             8833811                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total         8833811                       # number of ReadReq hits
system.cpu.icache.demand_hits::0              8833811                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::1                    0                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total          8833811                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::0             8833811                       # number of overall hits
system.cpu.icache.overall_hits::1                   0                       # number of overall hits
system.cpu.icache.overall_hits::total         8833811                       # number of overall hits
system.cpu.icache.ReadReq_misses::0           1095865                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1095865                       # number of ReadReq misses
system.cpu.icache.demand_misses::0            1095865                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::1                  0                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1095865                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::0           1095865                       # number of overall misses
system.cpu.icache.overall_misses::1                 0                       # number of overall misses
system.cpu.icache.overall_misses::total       1095865                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency    16411974488                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency     16411974488                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency    16411974488                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::0         9929676                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total      9929676                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::0          9929676                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::1                0                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total      9929676                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::0         9929676                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total      9929676                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::0       0.110363                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::0        0.110363                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::0       0.110363                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::0 14976.273983                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::0 14976.273983                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::0 14976.273983                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs      2523491                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               250                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 10093.964000                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.writebacks                     1562                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits             63554                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits              63554                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits             63554                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses         1032311                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses          1032311                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses         1032311                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency  12460934991                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency  12460934991                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency  12460934991                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::0     0.103962                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::0     0.103962                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::0     0.103962                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 12070.911761                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 12070.911761                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 12070.911761                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.itb_walker_cache.replacements        11904                       # number of replacements
system.cpu.itb_walker_cache.tagsinuse        6.021281                       # Cycle average of tags in use
system.cpu.itb_walker_cache.total_refs          25742                       # Total number of references to valid blocks.
system.cpu.itb_walker_cache.sampled_refs        11916                       # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.avg_refs         2.160289                       # Average number of references to valid blocks.
system.cpu.itb_walker_cache.warmup_cycle 5113551809500                       # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.occ_blocks::1     6.021281                       # Average occupied blocks per context
system.cpu.itb_walker_cache.occ_percent::1     0.376330                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.ReadReq_hits::1        25787                       # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total        25787                       # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::1            3                       # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total            3                       # number of WriteReq hits
system.cpu.itb_walker_cache.demand_hits::0            0                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::1        25790                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total        25790                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::0            0                       # number of overall hits
system.cpu.itb_walker_cache.overall_hits::1        25790                       # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total        25790                       # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::1        12756                       # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total        12756                       # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::0            0                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::1        12756                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total        12756                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::0            0                       # number of overall misses
system.cpu.itb_walker_cache.overall_misses::1        12756                       # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total        12756                       # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency    165450000                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency    165450000                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency    165450000                       # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::1        38543                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total        38543                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::1            3                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total            3                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.demand_accesses::0            0                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::1        38546                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total        38546                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::0            0                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::1        38546                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total        38546                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::1     0.330955                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::0     no_value                       # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::1     0.330929                       # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::0     no_value                       # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::1     0.330929                       # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::1 12970.366886                       # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::0          inf                       # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::1 12970.366886                       # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::0          inf                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::1 12970.366886                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.itb_walker_cache.writebacks           2156                       # number of writebacks
system.cpu.itb_walker_cache.demand_mshr_hits            0                       # number of demand (read+write) MSHR hits
system.cpu.itb_walker_cache.overall_mshr_hits            0                       # number of overall MSHR hits
system.cpu.itb_walker_cache.ReadReq_mshr_misses        12756                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses        12756                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses        12756                       # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency    126704000                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency    126704000                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency    126704000                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::1     0.330955                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::0          inf                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::1     0.330929                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::1     0.330929                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency  9932.894324                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency  9932.894324                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency  9932.894324                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.itb_walker_cache.mshr_cap_events            0                       # number of times MSHR cap was activated
system.cpu.itb_walker_cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.replacements       123389                       # number of replacements
system.cpu.dtb_walker_cache.tagsinuse       13.858352                       # Cycle average of tags in use
system.cpu.dtb_walker_cache.total_refs         128795                       # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.sampled_refs       123405                       # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.avg_refs         1.043677                       # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.warmup_cycle 5101298251000                       # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.occ_blocks::1    13.858352                       # Average occupied blocks per context
system.cpu.dtb_walker_cache.occ_percent::1     0.866147                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.ReadReq_hits::1       128795                       # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total       128795                       # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::0            0                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::1       128795                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total       128795                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::0            0                       # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::1       128795                       # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total       128795                       # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::1       124284                       # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total       124284                       # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::0            0                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::1       124284                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total       124284                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::0            0                       # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::1       124284                       # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total       124284                       # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency   1723739000                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency   1723739000                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency   1723739000                       # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::1       253079                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total       253079                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::0            0                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::1       253079                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total       253079                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::0            0                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::1       253079                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total       253079                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::1     0.491088                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::0     no_value                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::1     0.491088                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::0     no_value                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::1     0.491088                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::1 13869.355669                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::0          inf                       # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 13869.355669                       # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::0          inf                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 13869.355669                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.dtb_walker_cache.writebacks          38359                       # number of writebacks
system.cpu.dtb_walker_cache.demand_mshr_hits            0                       # number of demand (read+write) MSHR hits
system.cpu.dtb_walker_cache.overall_mshr_hits            0                       # number of overall MSHR hits
system.cpu.dtb_walker_cache.ReadReq_mshr_misses       124284                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses       124284                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses       124284                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency   1347076500                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency   1347076500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency   1347076500                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::1     0.491088                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::0          inf                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1     0.491088                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1     0.491088                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency 10838.696051                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency 10838.696051                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency 10838.696051                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.dtb_walker_cache.mshr_cap_events            0                       # number of times MSHR cap was activated
system.cpu.dtb_walker_cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                1658768                       # number of replacements
system.cpu.dcache.tagsinuse                511.997453                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 17937343                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                1659280                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                  10.810317                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle               13135000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0            511.997453                       # Average occupied blocks per context
system.cpu.dcache.occ_percent::0             0.999995                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::0            11377605                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        11377605                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::0            6537446                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        6537446                       # number of WriteReq hits
system.cpu.dcache.demand_hits::0             17915051                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::1                    0                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         17915051                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::0            17915051                       # number of overall hits
system.cpu.dcache.overall_hits::1                   0                       # number of overall hits
system.cpu.dcache.overall_hits::total        17915051                       # number of overall hits
system.cpu.dcache.ReadReq_misses::0           2443873                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       2443873                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::0          1875033                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1875033                       # number of WriteReq misses
system.cpu.dcache.demand_misses::0            4318906                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::1                  0                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        4318906                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::0           4318906                       # number of overall misses
system.cpu.dcache.overall_misses::1                 0                       # number of overall misses
system.cpu.dcache.overall_misses::total       4318906                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency    36695573000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency   63002180530                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency     99697753530                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency    99697753530                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::0        13821478                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     13821478                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::0        8412479                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      8412479                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::0         22233957                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::1                0                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     22233957                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::0        22233957                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     22233957                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::0       0.176817                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::0      0.222887                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::0        0.194248                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::0       0.194248                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::0 15015.335494                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::0 33600.571579                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::0 23084.029504                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::0 23084.029504                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs   1066704607                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets      6645500                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs             69708                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets             391                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 15302.470405                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 16996.163683                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks                  1546279                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits           1076649                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits          1578166                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits            2654815                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits           2654815                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses         1367224                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses         296867                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses          1664091                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses         1664091                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency  18012012500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency   9730106607                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency  27742119107                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency  27742119107                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency  86947466500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency   1385748000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency  88333214500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::0     0.098920                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::0     0.035289                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::0     0.074845                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::0     0.074845                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13174.148859                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32775.979166                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 16671.034882                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 16671.034882                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------