path: root/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  5.147635                       # Number of seconds simulated
sim_ticks                                5147635094500                       # Number of ticks simulated
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 351632                       # Simulator instruction rate (inst/s)
host_tick_rate                             2155130798                       # Simulator tick rate (ticks/s)
host_mem_usage                                 384428                       # Number of bytes of host memory used
host_seconds                                  2388.55                       # Real time elapsed on the host
sim_insts                                   839890138                       # Number of instructions simulated
system.l2c.replacements                        168889                       # number of replacements
system.l2c.tagsinuse                     38220.032298                       # Cycle average of tags in use
system.l2c.total_refs                         3756292                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        202498                       # Sample count of references to valid blocks.
system.l2c.avg_refs                         18.549773                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::0                 11771.329873                       # Average occupied blocks per context
system.l2c.occ_blocks::1                 26448.702425                       # Average occupied blocks per context
system.l2c.occ_percent::0                    0.179616                       # Average percentage of cache occupancy
system.l2c.occ_percent::1                    0.403575                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::0                    2324685                       # number of ReadReq hits
system.l2c.ReadReq_hits::1                     121813                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                2446498                       # number of ReadReq hits
system.l2c.Writeback_hits::0                  1589010                       # number of Writeback hits
system.l2c.Writeback_hits::total              1589010                       # number of Writeback hits
system.l2c.UpgradeReq_hits::0                     347                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 347                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::0                   150926                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               150926                       # number of ReadExReq hits
system.l2c.demand_hits::0                     2475611                       # number of demand (read+write) hits
system.l2c.demand_hits::1                      121813                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2597424                       # number of demand (read+write) hits
system.l2c.overall_hits::0                    2475611                       # number of overall hits
system.l2c.overall_hits::1                     121813                       # number of overall hits
system.l2c.overall_hits::total                2597424                       # number of overall hits
system.l2c.ReadReq_misses::0                    64844                       # number of ReadReq misses
system.l2c.ReadReq_misses::1                       78                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                64922                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::0                  3952                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              3952                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::0                 141925                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             141925                       # number of ReadExReq misses
system.l2c.demand_misses::0                    206769                       # number of demand (read+write) misses
system.l2c.demand_misses::1                        78                       # number of demand (read+write) misses
system.l2c.demand_misses::total                206847                       # number of demand (read+write) misses
system.l2c.overall_misses::0                   206769                       # number of overall misses
system.l2c.overall_misses::1                       78                       # number of overall misses
system.l2c.overall_misses::total               206847                       # number of overall misses
system.l2c.ReadReq_miss_latency            3405563500                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency           38740500                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency          7426067500                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency            10831631000                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency           10831631000                       # number of overall miss cycles
system.l2c.ReadReq_accesses::0                2389529                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::1                 121891                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2511420                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::0              1589010                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total          1589010                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::0                4299                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            4299                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::0               292851                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           292851                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::0                 2682380                       # number of demand (read+write) accesses
system.l2c.demand_accesses::1                  121891                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2804271                       # number of demand (read+write) accesses
system.l2c.overall_accesses::0                2682380                       # number of overall (read+write) accesses
system.l2c.overall_accesses::1                 121891                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2804271                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::0              0.027137                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::1              0.000640                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.027777                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::0           0.919284                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::0            0.484632                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::0               0.077084                       # miss rate for demand accesses
system.l2c.demand_miss_rate::1               0.000640                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.077724                       # miss rate for demand accesses
system.l2c.overall_miss_rate::0              0.077084                       # miss rate for overall accesses
system.l2c.overall_miss_rate::1              0.000640                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.077724                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::0   52519.331010                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::1   43661070.512821                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 43713589.843830                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::0  9802.758097                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::1          inf                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::0 52323.885855                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::1          inf                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::0    52385.178629                       # average overall miss latency
system.l2c.demand_avg_miss_latency::1    138867064.102564                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 138919449.281193                       # average overall miss latency
system.l2c.overall_avg_miss_latency::0   52385.178629                       # average overall miss latency
system.l2c.overall_avg_miss_latency::1   138867064.102564                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 138919449.281193                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks                          142854                       # number of writebacks
system.l2c.ReadReq_mshr_hits                        2                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits                         2                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits                        2                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses                  64920                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses                3952                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses               141925                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses                  206845                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses                 206845                       # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency       2614002500                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency     158446500                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency     5695372500                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency        8309375000                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency       8309375000                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency  61532786000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency   1222293500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency  62755079500                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::0         0.027169                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::1         0.532607                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.559776                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::0      0.919284                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::1           inf                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::0       0.484632                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::1            inf                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::0          0.077112                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::1          1.696967                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      1.774079                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::0         0.077112                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::1         1.696967                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     1.774079                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency 40264.979975                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency 40092.737854                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency 40129.452175                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency  40171.988687                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency 40171.988687                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.iocache.replacements                     47572                       # number of replacements
system.iocache.tagsinuse                     0.153668                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                     47588                       # Sample count of references to valid blocks.
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.warmup_cycle              4994556805000                       # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::1                 0.153668                       # Average occupied blocks per context
system.iocache.occ_percent::1                0.009604                       # Average percentage of cache occupancy
system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
system.iocache.overall_hits::0                      0                       # number of overall hits
system.iocache.overall_hits::1                      0                       # number of overall hits
system.iocache.overall_hits::total                  0                       # number of overall hits
system.iocache.ReadReq_misses::1                  907                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              907                       # number of ReadReq misses
system.iocache.WriteReq_misses::1               46720                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
system.iocache.demand_misses::1                 47627                       # number of demand (read+write) misses
system.iocache.demand_misses::total             47627                       # number of demand (read+write) misses
system.iocache.overall_misses::0                    0                       # number of overall misses
system.iocache.overall_misses::1                47627                       # number of overall misses
system.iocache.overall_misses::total            47627                       # number of overall misses
system.iocache.ReadReq_miss_latency         113709932                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency       6375573160                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency         6489283092                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency        6489283092                       # number of overall miss cycles
system.iocache.ReadReq_accesses::1                907                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            907                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::1             46720                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
system.iocache.demand_accesses::1               47627                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           47627                       # number of demand (read+write) accesses
system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
system.iocache.overall_accesses::1              47627                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          47627                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::1                 1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::1                1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
system.iocache.demand_miss_rate::1                  1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
system.iocache.overall_miss_rate::1                 1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::1 125369.274531                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::0          inf                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::1 136463.466610                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::0          inf                       # average overall miss latency
system.iocache.demand_avg_miss_latency::1 136252.190816                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.iocache.overall_avg_miss_latency::0          inf                       # average overall miss latency
system.iocache.overall_avg_miss_latency::1 136252.190816                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs      68827406                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                11262                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs  6111.472740                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks                       46667                       # number of writebacks
system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
system.iocache.ReadReq_mshr_misses                907                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses             46720                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses               47627                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses              47627                       # number of overall MSHR misses
system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.iocache.ReadReq_mshr_miss_latency     66523980                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency   3945823756                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency    4012347736                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency   4012347736                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::1            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::0          inf                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::1            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::0           inf                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::1             1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::1            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency 73345.071665                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency 84456.844092                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency 84245.233502                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency 84245.233502                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs           32                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
system.cpu.numCycles                        449675417                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.BPredUnit.lookups                 91353557                       # Number of BP lookups
system.cpu.BPredUnit.condPredicted           91353557                       # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect            1252427                       # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups              90165441                       # Number of BTB lookups
system.cpu.BPredUnit.BTBHits                 83892399                       # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles           28404587                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      452020244                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    91353557                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           83892399                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     171490466                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 6282228                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                     138765                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.BlockedCycles               82802558                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                39799                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles         48979                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles          284                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                   9973165                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                538692                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                    4066                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          287848736                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              3.084298                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.403265                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                116937192     40.62%     40.62% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  1491081      0.52%     41.14% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 72826914     25.30%     66.44% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  1443953      0.50%     66.94% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  1857439      0.65%     67.59% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  4043841      1.40%     68.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  1607058      0.56%     69.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  2086920      0.73%     70.28% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 85554338     29.72%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            287848736                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.203154                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.005214                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 33515134                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              79162809                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 165880226                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               4367269                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                4923298                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts              883825801                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                   605                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                4923298                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 37698163                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                52621688                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       10095648                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 165755555                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              16754384                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              879127879                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                 13400                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents               11681979                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               2180375                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands           881488672                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            1726997540                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       1726996684                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups               856                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             843288974                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 38199691                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts             489429                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         491577                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  43341957                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             19857410                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            10789691                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           3385955                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          3355339                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  872068801                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded              901279                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 866609285                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            183699                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        32269790                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     48278487                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         149791                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     287848736                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         3.010641                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.369672                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            82414213     28.63%     28.63% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            23159181      8.05%     36.68% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            14360314      4.99%     41.67% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             9848044      3.42%     45.09% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            79584318     27.65%     72.73% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             4908294      1.71%     74.44% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            72848439     25.31%     99.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              591496      0.21%     99.95% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              134437      0.05%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       287848736                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  190888      9.04%      9.04% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%      9.04% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      9.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      9.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      9.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      9.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      9.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      9.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      9.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      9.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      9.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      9.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      9.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      9.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      9.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      9.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      9.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      9.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      9.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      9.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      9.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      9.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      9.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      9.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      9.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      9.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      9.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      9.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.04% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                1791204     84.82%     93.86% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                129613      6.14%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass            300110      0.03%      0.03% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             831340529     95.93%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                    0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     95.96% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             25503279      2.94%     98.91% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite             9465367      1.09%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              866609285                       # Type of FU issued
system.cpu.iq.rate                           1.927188                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     2111705                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.002437                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         2023502478                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         905270549                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    855795997                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 118                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                426                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           39                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              868420821                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                      59                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          1311302                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      4519097                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        14074                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        32279                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      2365528                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads      7816755                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked        157456                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                4923298                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                33675049                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               6020092                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           872970080                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            307769                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              19857410                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             10789736                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts             900477                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                5569363                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 25535                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          32279                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         904299                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       527474                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              1431773                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             864483471                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              25041287                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           2125813                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                     34281165                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 86747902                       # Number of branches executed
system.cpu.iew.exec_stores                    9239878                       # Number of stores executed
system.cpu.iew.exec_rate                     1.922461                       # Inst execution rate
system.cpu.iew.wb_sent                      863862887                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     855796036                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 671971409                       # num instructions producing a value
system.cpu.iew.wb_consumers                1172569006                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.903142                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.573076                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts      839890138                       # The number of committed instructions
system.cpu.commit.commitSquashedInsts        32974049                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls          751486                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           1258131                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    282941233                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     2.968426                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.859611                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    102772882     36.32%     36.32% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     13081684      4.62%     40.95% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      4919909      1.74%     42.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     76957003     27.20%     69.88% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      4031247      1.42%     71.31% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1851904      0.65%     71.96% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      1144492      0.40%     72.37% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7     71610729     25.31%     97.68% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      6571383      2.32%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    282941233                       # Number of insts commited each cycle
system.cpu.commit.count                     839890138                       # Number of instructions committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       23762518                       # Number of memory references committed
system.cpu.commit.loads                      15338310                       # Number of loads committed
system.cpu.commit.membars                         801                       # Number of memory barriers committed
system.cpu.commit.branches                   85528433                       # Number of branches committed
system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 768507409                       # Number of committed integer instructions.
system.cpu.commit.function_calls                    0                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               6571383                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   1149152761                       # The number of ROB reads
system.cpu.rob.rob_writes                  1750664129                       # The number of ROB writes
system.cpu.timesIdled                         3067558                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                       161826681                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   839890138                       # Number of Instructions Simulated
system.cpu.committedInsts_total             839890138                       # Number of Instructions Simulated
system.cpu.cpi                               0.535398                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.535398                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.867770                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.867770                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               1406887924                       # number of integer regfile reads
system.cpu.int_regfile_writes               857851212                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        39                       # number of floating regfile reads
system.cpu.misc_regfile_reads               282323555                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 407360                       # number of misc regfile writes
system.cpu.icache.replacements                1023301                       # number of replacements
system.cpu.icache.tagsinuse                510.501366                       # Cycle average of tags in use
system.cpu.icache.total_refs                  8883561                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                1023813                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                   8.676937                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle            54617484000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0            510.501366                       # Average occupied blocks per context
system.cpu.icache.occ_percent::0             0.997073                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::0             8883561                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total         8883561                       # number of ReadReq hits
system.cpu.icache.demand_hits::0              8883561                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::1                    0                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total          8883561                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::0             8883561                       # number of overall hits
system.cpu.icache.overall_hits::1                   0                       # number of overall hits
system.cpu.icache.overall_hits::total         8883561                       # number of overall hits
system.cpu.icache.ReadReq_misses::0           1089602                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1089602                       # number of ReadReq misses
system.cpu.icache.demand_misses::0            1089602                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::1                  0                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1089602                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::0           1089602                       # number of overall misses
system.cpu.icache.overall_misses::1                 0                       # number of overall misses
system.cpu.icache.overall_misses::total       1089602                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency    16315202989                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency     16315202989                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency    16315202989                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::0         9973163                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total      9973163                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::0          9973163                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::1                0                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total      9973163                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::0         9973163                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total      9973163                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::0       0.109253                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::0        0.109253                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::0       0.109253                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::0 14973.543541                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::0 14973.543541                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::0 14973.543541                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs      2502991                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               249                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 10052.172691                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.writebacks                     1566                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits             63225                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits              63225                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits             63225                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses         1026377                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses          1026377                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses         1026377                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency  12387818491                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency  12387818491                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency  12387818491                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::0     0.102914                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::0     0.102914                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::0     0.102914                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 12069.462284                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 12069.462284                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 12069.462284                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.itb_walker_cache.replacements        10573                       # number of replacements
system.cpu.itb_walker_cache.tagsinuse        6.015451                       # Cycle average of tags in use
system.cpu.itb_walker_cache.total_refs          26778                       # Total number of references to valid blocks.
system.cpu.itb_walker_cache.sampled_refs        10582                       # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.avg_refs         2.530524                       # Average number of references to valid blocks.
system.cpu.itb_walker_cache.warmup_cycle 5110516160500                       # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.occ_blocks::1     6.015451                       # Average occupied blocks per context
system.cpu.itb_walker_cache.occ_percent::1     0.375966                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.ReadReq_hits::1        26928                       # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total        26928                       # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::1            3                       # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total            3                       # number of WriteReq hits
system.cpu.itb_walker_cache.demand_hits::0            0                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::1        26931                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total        26931                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::0            0                       # number of overall hits
system.cpu.itb_walker_cache.overall_hits::1        26931                       # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total        26931                       # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::1        11444                       # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total        11444                       # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::0            0                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::1        11444                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total        11444                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::0            0                       # number of overall misses
system.cpu.itb_walker_cache.overall_misses::1        11444                       # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total        11444                       # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency    147254000                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency    147254000                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency    147254000                       # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::1        38372                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total        38372                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::1            3                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total            3                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.demand_accesses::0            0                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::1        38375                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total        38375                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::0            0                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::1        38375                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total        38375                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::1     0.298238                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::0     no_value                       # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::1     0.298215                       # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::0     no_value                       # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::1     0.298215                       # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::1 12867.354072                       # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::0          inf                       # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::1 12867.354072                       # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::0          inf                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::1 12867.354072                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.itb_walker_cache.writebacks           1953                       # number of writebacks
system.cpu.itb_walker_cache.demand_mshr_hits            0                       # number of demand (read+write) MSHR hits
system.cpu.itb_walker_cache.overall_mshr_hits            0                       # number of overall MSHR hits
system.cpu.itb_walker_cache.ReadReq_mshr_misses        11444                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses        11444                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses        11444                       # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency    112503000                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency    112503000                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency    112503000                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::1     0.298238                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::0          inf                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::1     0.298215                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::1     0.298215                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency  9830.741000                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency  9830.741000                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency  9830.741000                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.itb_walker_cache.mshr_cap_events            0                       # number of times MSHR cap was activated
system.cpu.itb_walker_cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.replacements       121016                       # number of replacements
system.cpu.dtb_walker_cache.tagsinuse       13.855490                       # Cycle average of tags in use
system.cpu.dtb_walker_cache.total_refs         127830                       # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.sampled_refs       121032                       # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.avg_refs         1.056167                       # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.warmup_cycle 5101318853000                       # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.occ_blocks::1    13.855490                       # Average occupied blocks per context
system.cpu.dtb_walker_cache.occ_percent::1     0.865968                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.ReadReq_hits::1       127830                       # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total       127830                       # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::0            0                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::1       127830                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total       127830                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::0            0                       # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::1       127830                       # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total       127830                       # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::1       121934                       # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total       121934                       # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::0            0                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::1       121934                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total       121934                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::0            0                       # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::1       121934                       # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total       121934                       # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency   1683985000                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency   1683985000                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency   1683985000                       # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::1       249764                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total       249764                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::0            0                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::1       249764                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total       249764                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::0            0                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::1       249764                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total       249764                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::1     0.488197                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::0     no_value                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::1     0.488197                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::0     no_value                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::1     0.488197                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::1 13810.627061                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::0          inf                       # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 13810.627061                       # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::0          inf                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 13810.627061                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.dtb_walker_cache.writebacks          38699                       # number of writebacks
system.cpu.dtb_walker_cache.demand_mshr_hits            0                       # number of demand (read+write) MSHR hits
system.cpu.dtb_walker_cache.overall_mshr_hits            0                       # number of overall MSHR hits
system.cpu.dtb_walker_cache.ReadReq_mshr_misses       121934                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses       121934                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses       121934                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency   1314199000                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency   1314199000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency   1314199000                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::1     0.488197                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::0          inf                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1     0.488197                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1     0.488197                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency 10777.953647                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency 10777.953647                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency 10777.953647                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.dtb_walker_cache.mshr_cap_events            0                       # number of times MSHR cap was activated
system.cpu.dtb_walker_cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                1658649                       # number of replacements
system.cpu.dcache.tagsinuse                511.998343                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 17949632                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                1659161                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                  10.818499                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle               13135000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0            511.998343                       # Average occupied blocks per context
system.cpu.dcache.occ_percent::0             0.999997                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::0            11386734                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        11386734                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::0            6540638                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        6540638                       # number of WriteReq hits
system.cpu.dcache.demand_hits::0             17927372                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::1                    0                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         17927372                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::0            17927372                       # number of overall hits
system.cpu.dcache.overall_hits::1                   0                       # number of overall hits
system.cpu.dcache.overall_hits::total        17927372                       # number of overall hits
system.cpu.dcache.ReadReq_misses::0           2451014                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       2451014                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::0          1874260                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1874260                       # number of WriteReq misses
system.cpu.dcache.demand_misses::0            4325274                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::1                  0                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        4325274                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::0           4325274                       # number of overall misses
system.cpu.dcache.overall_misses::1                 0                       # number of overall misses
system.cpu.dcache.overall_misses::total       4325274                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency    36760499500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency   62950533530                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency     99711033030                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency    99711033030                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::0        13837748                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     13837748                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::0        8414898                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      8414898                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::0         22252646                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::1                0                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     22252646                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::0        22252646                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     22252646                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::0       0.177125                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::0      0.222731                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::0        0.194371                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::0       0.194371                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::0 14998.078142                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::0 33586.873502                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::0 23053.113636                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::0 23053.113636                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs   1060124132                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets      6661500                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs             70229                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets             395                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 15095.247433                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 16864.556962                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks                  1546792                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits           1084106                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits          1577234                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits            2661340                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits           2661340                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses         1366908                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses         297026                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses          1663934                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses         1663934                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency  18014700500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency   9717717632                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency  27732418132                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency  27732418132                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency  86947187500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency   1385675500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency  88332863000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::0     0.098781                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::0     0.035298                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::0     0.074775                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::0     0.074775                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13179.160924                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32716.723896                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 16666.777728                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 16666.777728                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------