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|
---------- Begin Simulation Statistics ----------
host_inst_rate 109166 # Simulator instruction rate (inst/s)
host_mem_usage 384348 # Number of bytes of host memory used
host_seconds 835.45 # Real time elapsed on the host
host_tick_rate 67095197 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 91202735 # Number of instructions simulated
sim_seconds 0.056055 # Number of seconds simulated
sim_ticks 56054650500 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 20717891 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 22133087 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 1885128 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 22369136 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 22369136 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 18672384 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 365812 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 109380669 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 0.833810 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 1.220278 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 55493598 50.73% 50.73% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 34988156 31.99% 82.72% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 8951301 8.18% 90.91% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 6346851 5.80% 96.71% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 1763725 1.61% 98.32% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 198423 0.18% 98.50% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 611708 0.56% 99.06% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 661095 0.60% 99.67% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 365812 0.33% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 109380669 # Number of insts commited each cycle
system.cpu.commit.COM:count 91202735 # Number of instructions committed
system.cpu.commit.COM:loads 22585492 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 27330336 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 1941616 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 91202735 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 544722 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 11836568 # The number of squashed insts skipped by commit
system.cpu.committedInsts 91202735 # Number of Instructions Simulated
system.cpu.committedInsts_total 91202735 # Number of Instructions Simulated
system.cpu.cpi 1.229232 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.229232 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 23356359 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 5257.244166 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2204.745551 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 22405801 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 4997315500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.040698 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 950558 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 47017 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 1992078000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.038685 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 903541 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 4738868 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 21505.165872 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20098.081505 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 4602377 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 2935261595 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.028802 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 136491 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 89917 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 936048048 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.009828 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 46574 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2906.794309 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 28.426220 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 6009 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 17466927 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 28095227 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 7297.350069 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 3081.864877 # average overall mshr miss latency
system.cpu.dcache.demand_hits 27008178 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 7932577095 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.038692 # miss rate for demand accesses
system.cpu.dcache.demand_misses 1087049 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 136934 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 2928126048 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.033818 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 950115 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.851200 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 3486.513521 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 28095227 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 7297.350069 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 3081.864877 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 27008178 # number of overall hits
system.cpu.dcache.overall_miss_latency 7932577095 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.038692 # miss rate for overall accesses
system.cpu.dcache.overall_misses 1087049 # number of overall misses
system.cpu.dcache.overall_mshr_hits 136934 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 2928126048 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.033818 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 950115 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 946019 # number of replacements
system.cpu.dcache.sampled_refs 950115 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 3486.513521 # Cycle average of tags in use
system.cpu.dcache.total_refs 27008178 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 23888323000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 943195 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 6646244 # Number of cycles decode is blocked
system.cpu.decode.DECODE:DecodedInsts 108354442 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 27877026 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 74250528 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 2697133 # Number of cycles decode is squashing
system.cpu.decode.DECODE:UnblockCycles 606871 # Number of cycles decode is unblocking
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.fetch.Branches 22369136 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 12683523 # Number of cache lines fetched
system.cpu.fetch.Cycles 76804790 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 214313 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 109645009 # Number of instructions fetch has processed
system.cpu.fetch.MiscStallCycles 18268 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.SquashCycles 1945737 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.199530 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 12683523 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 20717891 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 0.978019 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 112077802 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.986563 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.108840 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 35656336 31.81% 31.81% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 60887091 54.33% 86.14% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 7618220 6.80% 92.94% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 828250 0.74% 93.68% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 4141724 3.70% 97.37% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 2560072 2.28% 99.66% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 241811 0.22% 99.87% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 9014 0.01% 99.88% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 135284 0.12% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 112077802 # Number of instructions fetched each cycle (Total)
system.cpu.icache.ReadReq_accesses 12683523 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 36326.451613 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34504.457652 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 12682748 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 28153000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000061 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 775 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 102 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 23221500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000053 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 673 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 18845.093611 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 12683523 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 36326.451613 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 34504.457652 # average overall mshr miss latency
system.cpu.icache.demand_hits 12682748 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 28153000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000061 # miss rate for demand accesses
system.cpu.icache.demand_misses 775 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 102 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 23221500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000053 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 673 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.278329 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 570.018362 # Average occupied blocks per context
system.cpu.icache.overall_accesses 12683523 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 36326.451613 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 34504.457652 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 12682748 # number of overall hits
system.cpu.icache.overall_miss_latency 28153000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000061 # miss rate for overall accesses
system.cpu.icache.overall_misses 775 # number of overall misses
system.cpu.icache.overall_mshr_hits 102 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 23221500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000053 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 673 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 3 # number of replacements
system.cpu.icache.sampled_refs 673 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 570.018362 # Cycle average of tags in use
system.cpu.icache.total_refs 12682748 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 31500 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 19532471 # Number of branches executed
system.cpu.iew.EXEC:nop 0 # number of nop insts executed
system.cpu.iew.EXEC:rate 0.868515 # Inst execution rate
system.cpu.iew.EXEC:refs 28649530 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 5007242 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 90073384 # num instructions consuming a value
system.cpu.iew.WB:count 96607772 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.596776 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 53753594 # num instructions producing a value
system.cpu.iew.WB:rate 0.861728 # insts written-back per cycle
system.cpu.iew.WB:sent 96877677 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 2055865 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 89156 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 24681131 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 553822 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 1090188 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 5533285 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 103041048 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 23642288 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 2271319 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 97368620 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 1607 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 2697133 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 23177 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 17440 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 113868 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 30334 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 1330 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 2095638 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 788441 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 1330 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 76117 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 1979748 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 0.813516 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.813516 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 70327801 70.58% 70.58% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 10479 0.01% 70.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 70.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 70.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 70.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 70.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 70.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 70.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 70.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 70.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 70.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 70.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 70.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 70.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 70.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 70.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 70.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 70.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 70.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 2 0.00% 70.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 11 0.00% 70.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 70.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 27 0.00% 70.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 70.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 3 0.00% 70.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 70.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 24261779 24.35% 94.94% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 5039837 5.06% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total 99639939 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 491330 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.004931 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 430175 87.55% 87.55% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 27 0.01% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 26408 5.37% 92.93% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 34720 7.07% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples 112077802 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.889025 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.090069 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 47848976 42.69% 42.69% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 42741533 38.14% 80.83% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 14042267 12.53% 93.36% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 4560980 4.07% 97.43% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 789415 0.70% 98.13% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 737896 0.66% 98.79% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 1220893 1.09% 99.88% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 128302 0.11% 99.99% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 7540 0.01% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 112077802 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 0.888775 # Inst issue rate
system.cpu.iq.iqInstsAdded 102487226 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 99639939 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 553822 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 9797863 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 388 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 9100 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 13596507 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 46574 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34284.629133 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31026.465938 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 32027 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 498738500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.312342 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 14547 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 451342000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.312342 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 14547 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 904214 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34294.794795 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31103.850051 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 903215 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 34260500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.001105 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 999 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_hits 12 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_miss_latency 30699500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001092 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 987 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 943195 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 943195 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 103.008184 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 950788 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34285.282388 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31031.382773 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 935242 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 532999000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.016351 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 15546 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 12 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 482041500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.016338 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 15534 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.012324 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.246682 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 403.843593 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 8083.268341 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 950788 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34285.282388 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31031.382773 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 935242 # number of overall hits
system.cpu.l2cache.overall_miss_latency 532999000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.016351 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 15546 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 12 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 482041500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.016338 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 15534 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 709 # number of replacements
system.cpu.l2cache.sampled_refs 15518 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 8487.111934 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1598481 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 32 # number of writebacks
system.cpu.memDep0.conflictingLoads 436025 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 249497 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 24681131 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 5533285 # Number of stores inserted to the mem dependence unit.
system.cpu.numCycles 112109302 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 294826 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 72061910 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 4906 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 29931124 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 31548 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 277459118 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 106593773 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 83924761 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 72730212 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 2697133 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 723330 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 11862848 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 5701177 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 592742 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 1065555 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 576556 # count of temporary serializing insts renamed
system.cpu.timesIdled 1292 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 442 # Number of system calls
---------- End Simulation Statistics ----------
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