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|
---------- Begin Simulation Statistics ----------
sim_seconds 0.033049 # Number of seconds simulated
sim_ticks 33049447500 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 142392 # Simulator instruction rate (inst/s)
host_tick_rate 51572715 # Simulator tick rate (ticks/s)
host_mem_usage 349636 # Number of bytes of host memory used
host_seconds 640.83 # Real time elapsed on the host
sim_insts 91249665 # Number of instructions simulated
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 442 # Number of system calls
system.cpu.numCycles 66098896 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 27480852 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 21948199 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 1405962 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 24356195 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 23358870 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 118630 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 12953 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 15359689 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 131196018 # Number of instructions fetch has processed
system.cpu.fetch.Branches 27480852 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 23477500 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 32529765 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 5482056 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 14124387 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 126 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 14730221 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 368829 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 66068188 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.007516 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.747063 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 33589573 50.84% 50.84% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 6678757 10.11% 60.95% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 5691945 8.62% 69.56% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 4809462 7.28% 76.84% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 2791705 4.23% 81.07% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 1680164 2.54% 83.61% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 1554358 2.35% 85.97% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 2929699 4.43% 90.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 6342525 9.60% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 66068188 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.415754 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.984844 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 17938862 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 12617377 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 30503596 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 985227 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 4023126 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 4444811 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 31491 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 129102519 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 31918 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 4023126 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 19654279 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 1111044 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 8373205 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 29732459 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 3174075 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 125001528 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 20 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 255212 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 1879877 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 11 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 145677643 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 544340805 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 544335582 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 5223 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 107429087 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 38248551 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 647769 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 649953 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 7510284 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 29313185 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 5861466 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1226589 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 648810 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 117406606 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 634842 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 106217024 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 74725 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 26332148 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 63315965 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 80484 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 66068188 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.607688 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.762772 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 24256842 36.71% 36.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 14242052 21.56% 58.27% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 9853567 14.91% 73.19% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 8048166 12.18% 85.37% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 4234412 6.41% 91.78% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 2296375 3.48% 95.25% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 2457048 3.72% 98.97% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 476279 0.72% 99.69% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 203447 0.31% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 66068188 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 53590 10.28% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 27 0.01% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 193594 37.13% 47.41% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 274209 52.59% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 74732015 70.36% 70.36% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 10984 0.01% 70.37% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.37% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.37% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.37% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.37% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.37% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.37% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 117 0.00% 70.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 183 0.00% 70.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.37% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 26127838 24.60% 94.97% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 5345884 5.03% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 106217024 # Type of FU issued
system.cpu.iq.rate 1.606941 # Inst issue rate
system.cpu.iq.fu_busy_cnt 521420 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.004909 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 279097712 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 144373136 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 102515328 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 669 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 1008 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 309 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 106738111 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 333 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 366236 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 6737356 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 42339 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 715 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 1114761 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 30343 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 4023126 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 183340 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 29024 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 118080266 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 812187 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 29313185 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 5861466 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 629989 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 9572 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 1070 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 715 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 1280450 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 209997 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1490447 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 104523417 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 25726566 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1693607 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 38818 # number of nop insts executed
system.cpu.iew.exec_refs 30937872 # number of memory reference insts executed
system.cpu.iew.exec_branches 21209374 # Number of branches executed
system.cpu.iew.exec_stores 5211306 # Number of stores executed
system.cpu.iew.exec_rate 1.581319 # Inst execution rate
system.cpu.iew.wb_sent 102947388 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 102515637 # cumulative count of insts written-back
system.cpu.iew.wb_producers 60320212 # num instructions producing a value
system.cpu.iew.wb_consumers 97098710 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.550943 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.621226 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 91262274 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 26817270 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 554358 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 1387669 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 62045063 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.470903 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.226778 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 28329843 45.66% 45.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 16548650 26.67% 72.33% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 5280214 8.51% 80.84% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 3902195 6.29% 87.13% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 2034976 3.28% 90.41% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 672623 1.08% 91.50% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 530029 0.85% 92.35% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 208846 0.34% 92.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 4537687 7.31% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 62045063 # Number of insts commited each cycle
system.cpu.commit.count 91262274 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 27322533 # Number of memory references committed
system.cpu.commit.loads 22575828 # Number of loads committed
system.cpu.commit.membars 3888 # Number of memory barriers committed
system.cpu.commit.branches 18722422 # Number of branches committed
system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
system.cpu.commit.int_insts 72533126 # Number of committed integer instructions.
system.cpu.commit.function_calls 56148 # Number of function calls committed.
system.cpu.commit.bw_lim_events 4537687 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 175581186 # The number of ROB reads
system.cpu.rob.rob_writes 240196081 # The number of ROB writes
system.cpu.timesIdled 1543 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 30708 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 91249665 # Number of Instructions Simulated
system.cpu.committedInsts_total 91249665 # Number of Instructions Simulated
system.cpu.cpi 0.724374 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.724374 # CPI: Total CPI of All Threads
system.cpu.ipc 1.380502 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.380502 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 496839540 # number of integer regfile reads
system.cpu.int_regfile_writes 120902305 # number of integer regfile writes
system.cpu.fp_regfile_reads 158 # number of floating regfile reads
system.cpu.fp_regfile_writes 392 # number of floating regfile writes
system.cpu.misc_regfile_reads 184716876 # number of misc regfile reads
system.cpu.misc_regfile_writes 11506 # number of misc regfile writes
system.cpu.icache.replacements 2 # number of replacements
system.cpu.icache.tagsinuse 613.066905 # Cycle average of tags in use
system.cpu.icache.total_refs 14729300 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 718 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 20514.345404 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 613.066905 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.299349 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 14729300 # number of ReadReq hits
system.cpu.icache.demand_hits 14729300 # number of demand (read+write) hits
system.cpu.icache.overall_hits 14729300 # number of overall hits
system.cpu.icache.ReadReq_misses 921 # number of ReadReq misses
system.cpu.icache.demand_misses 921 # number of demand (read+write) misses
system.cpu.icache.overall_misses 921 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 32465000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 32465000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 32465000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 14730221 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 14730221 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 14730221 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000063 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000063 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000063 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 35249.728556 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 35249.728556 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 35249.728556 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 203 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 203 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 203 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 718 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 718 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 718 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 24779500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 24779500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 24779500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000049 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000049 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000049 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34511.838440 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 34511.838440 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 34511.838440 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 943500 # number of replacements
system.cpu.dcache.tagsinuse 3561.430485 # Cycle average of tags in use
system.cpu.dcache.total_refs 28801207 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 947596 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 30.393973 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 12279149000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 3561.430485 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.869490 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 24229442 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 4559293 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 6724 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits 5748 # number of StoreCondReq hits
system.cpu.dcache.demand_hits 28788735 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 28788735 # number of overall hits
system.cpu.dcache.ReadReq_misses 990132 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 175688 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses 7 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses 1165820 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 1165820 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 5482674500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 4505328405 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency 124500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency 9988002905 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 9988002905 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 25219574 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses 6731 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses 5748 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 29954555 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 29954555 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.039260 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.037104 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate 0.001040 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate 0.038920 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.038920 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 5537.316742 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 25643.916517 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency 17785.714286 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency 8567.362805 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 8567.362805 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 23285977 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 8139 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2861.036614 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 942954 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 87074 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 131149 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits 7 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits 218223 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 218223 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 903058 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 44539 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 947597 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 947597 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 2256691000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 1081795530 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 3338486530 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 3338486530 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.035808 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.009406 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.031634 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.031634 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2498.943589 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24288.725162 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 3523.107956 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 3523.107956 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 742 # number of replacements
system.cpu.l2cache.tagsinuse 9256.207068 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1596737 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 15558 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 102.631251 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 391.956879 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 8864.250189 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.011962 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.270515 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 901452 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 942954 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 31278 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 932730 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 932730 # number of overall hits
system.cpu.l2cache.ReadReq_misses 1045 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 14540 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 15585 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 15585 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 35800500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 498909000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 534709500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 534709500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 902497 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 942954 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 45818 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 948315 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 948315 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.001158 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.317343 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.016434 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.016434 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34258.851675 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34312.861073 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34309.239654 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34309.239654 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks 32 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits 10 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 10 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 1035 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 14540 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 15575 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 15575 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 32188500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 451730000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 483918500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 483918500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001147 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.317343 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.016424 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.016424 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31100 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31068.088033 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31070.208668 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31070.208668 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
|
