blob: 433654cb06225b931bcf16c311b8385d668fd0e0 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
|
---------- Begin Simulation Statistics ----------
host_inst_rate 2004505 # Simulator instruction rate (inst/s)
host_mem_usage 316136 # Number of bytes of host memory used
host_seconds 121.64 # Real time elapsed on the host
host_tick_rate 2987214089 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 243829010 # Number of instructions simulated
sim_seconds 0.363367 # Number of seconds simulated
sim_ticks 363367019000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 82219469 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 13898.235302 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11898.235302 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 81326625 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 12408956000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.010859 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 892844 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 10623268000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.010859 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 892844 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 3886 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_avg_miss_latency 25000 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 23000 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_hits 3878 # number of SwapReq hits
system.cpu.dcache.SwapReq_miss_latency 200000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_rate 0.002059 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_misses 8 # number of SwapReq misses
system.cpu.dcache.SwapReq_mshr_miss_latency 184000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_rate 0.002059 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_misses 8 # number of SwapReq MSHR misses
system.cpu.dcache.WriteReq_accesses 22901836 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 22806873 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 2374075000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.004147 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 94963 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 2184149000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.004147 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 94963 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 110.887563 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 105121305 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 14965.505407 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 12965.505407 # average overall mshr miss latency
system.cpu.dcache.demand_hits 104133498 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 14783031000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.009397 # miss rate for demand accesses
system.cpu.dcache.demand_misses 987807 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 12807417000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.009397 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 987807 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 105121305 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 14965.505407 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 12965.505407 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 104133498 # number of overall hits
system.cpu.dcache.overall_miss_latency 14783031000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.009397 # miss rate for overall accesses
system.cpu.dcache.overall_misses 987807 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 12807417000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.009397 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 987807 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 935465 # number of replacements
system.cpu.dcache.sampled_refs 939561 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 3566.815369 # Cycle average of tags in use
system.cpu.dcache.total_refs 104185630 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 134193669000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 94875 # number of writebacks
system.cpu.icache.ReadReq_accesses 244425341 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 24972.696246 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 22972.696246 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 244424462 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 21951000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 879 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 20193000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 879 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 278071.060296 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 244425341 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 24972.696246 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 22972.696246 # average overall mshr miss latency
system.cpu.icache.demand_hits 244424462 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 21951000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
system.cpu.icache.demand_misses 879 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 20193000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 879 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 244425341 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 24972.696246 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 22972.696246 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 244424462 # number of overall hits
system.cpu.icache.overall_miss_latency 21951000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
system.cpu.icache.overall_misses 879 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 20193000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 879 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 25 # number of replacements
system.cpu.icache.sampled_refs 879 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 716.847005 # Cycle average of tags in use
system.cpu.icache.total_refs 244424462 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadExReq_accesses 46717 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 1027774000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 46717 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 513887000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 46717 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 893723 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 826014 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1489598000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.075761 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 67709 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 744799000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.075761 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 67709 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 48254 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 1061588000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 48254 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 530794000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 48254 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 94875 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses
system.cpu.l2cache.Writeback_misses 94875 # number of Writeback misses
system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
system.cpu.l2cache.Writeback_mshr_misses 94875 # number of Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 48.787024 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 940440 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 826014 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 2517372000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.121673 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 114426 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 1258686000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.121673 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 114426 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 940440 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 826014 # number of overall hits
system.cpu.l2cache.overall_miss_latency 2517372000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.121673 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 114426 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 1258686000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.121673 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 114426 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 829 # number of replacements
system.cpu.l2cache.sampled_refs 11344 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 8106.277957 # Cycle average of tags in use
system.cpu.l2cache.total_refs 553440 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 726734038 # number of cpu cycles simulated
system.cpu.num_insts 243829010 # Number of instructions executed
system.cpu.num_refs 105710359 # Number of memory references
system.cpu.workload.PROG:num_syscalls 428 # Number of system calls
---------- End Simulation Statistics ----------
|
