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|
---------- Begin Simulation Statistics ----------
host_inst_rate 115680 # Simulator instruction rate (inst/s)
host_mem_usage 225512 # Number of bytes of host memory used
host_seconds 4956.26 # Real time elapsed on the host
host_tick_rate 67434212 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 573342252 # Number of instructions simulated
sim_seconds 0.334222 # Number of seconds simulated
sim_ticks 334221751500 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 146248863 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 176289381 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 2732047 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 15792639 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 173563787 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 218029317 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 10847475 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 116606323 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 7009812 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 605188855 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 0.949598 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 1.450627 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 311994753 51.55% 51.55% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 161715098 26.72% 78.27% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 68890759 11.38% 89.66% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 25427565 4.20% 93.86% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 17265141 2.85% 96.71% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 5227008 0.86% 97.58% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 5978308 0.99% 98.56% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 1680411 0.28% 98.84% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 7009812 1.16% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 605188855 # Number of insts commited each cycle
system.cpu.commit.COM:count 574686136 # Number of instructions committed
system.cpu.commit.COM:fp_insts 16 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 9757362 # Number of function calls committed.
system.cpu.commit.COM:int_insts 473702069 # Number of committed integer instructions.
system.cpu.commit.COM:loads 126773148 # Number of loads committed
system.cpu.commit.COM:membars 1488542 # Number of memory barriers committed
system.cpu.commit.COM:refs 184377217 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 21479549 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 574686136 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 3877864 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 397226721 # The number of squashed insts skipped by commit
system.cpu.committedInsts 573342252 # Number of Instructions Simulated
system.cpu.committedInsts_total 573342252 # Number of Instructions Simulated
system.cpu.cpi 1.165872 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.165872 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 2604331 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_avg_miss_latency 7833.333333 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_hits 2604295 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_miss_latency 282000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_rate 0.000014 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_misses 36 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_mshr_hits 36 # number of LoadLockedReq MSHR hits
system.cpu.dcache.ReadReq_accesses 142077585 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 10714.447779 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6999.796046 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 141007026 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 11470448500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.007535 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 1070559 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 219878 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 5954593500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.005987 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 850681 # number of ReadReq MSHR misses
system.cpu.dcache.StoreCondReq_accesses 2232133 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_hits 2232133 # number of StoreCondReq hits
system.cpu.dcache.WriteReq_accesses 54239306 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 15646.653056 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13092.754811 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 52838909 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 21911526000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.025819 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1400397 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 1056210 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 4506356000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006346 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 344187 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 166.282010 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 196316891 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 13509.740562 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 8754.899704 # average overall mshr miss latency
system.cpu.dcache.demand_hits 193845935 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 33381974500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.012587 # miss rate for demand accesses
system.cpu.dcache.demand_misses 2470956 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 1276088 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 10460949500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.006086 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 1194868 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.991141 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4059.712057 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 196316891 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 13509.740562 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 8754.899704 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 193845935 # number of overall hits
system.cpu.dcache.overall_miss_latency 33381974500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.012587 # miss rate for overall accesses
system.cpu.dcache.overall_misses 2470956 # number of overall misses
system.cpu.dcache.overall_mshr_hits 1276088 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 10460949500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.006086 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 1194868 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 1190756 # number of replacements
system.cpu.dcache.sampled_refs 1194852 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4059.712057 # Cycle average of tags in use
system.cpu.dcache.total_refs 198682392 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 6636207000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 1064084 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 88183325 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 76234 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 32910143 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 1105509065 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 280452015 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 231095248 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 58620851 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 216396 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 5458266 # Number of cycles decode is unblocking
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.fetch.Branches 218029317 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 124225331 # Number of cache lines fetched
system.cpu.fetch.Cycles 240845488 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 2943984 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 985167776 # Number of instructions fetch has processed
system.cpu.fetch.MiscStallCycles 5168276 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.SquashCycles 21620484 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.326175 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 124225331 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 157096338 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.473824 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 663809705 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.722895 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.715589 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 422975812 63.72% 63.72% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 19490823 2.94% 66.66% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 33888081 5.11% 71.76% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 39021858 5.88% 77.64% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 37073066 5.58% 83.22% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 16674783 2.51% 85.74% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 18304020 2.76% 88.49% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 13198645 1.99% 90.48% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 63182617 9.52% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 663809705 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
system.cpu.icache.ReadReq_accesses 124225331 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 14458.321717 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 10724.096566 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 124210983 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 207448000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000115 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 14348 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 1010 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 143038000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000107 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 13338 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 9323.748912 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 124225331 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 14458.321717 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 10724.096566 # average overall mshr miss latency
system.cpu.icache.demand_hits 124210983 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 207448000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000115 # miss rate for demand accesses
system.cpu.icache.demand_misses 14348 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 1010 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 143038000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000107 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 13338 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.515723 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1056.199986 # Average occupied blocks per context
system.cpu.icache.overall_accesses 124225331 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 14458.321717 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 10724.096566 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 124210983 # number of overall hits
system.cpu.icache.overall_miss_latency 207448000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000115 # miss rate for overall accesses
system.cpu.icache.overall_misses 14348 # number of overall misses
system.cpu.icache.overall_mshr_hits 1010 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 143038000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000107 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 13338 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 11505 # number of replacements
system.cpu.icache.sampled_refs 13322 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1056.199986 # Cycle average of tags in use
system.cpu.icache.total_refs 124210983 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 4633799 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 138142297 # Number of branches executed
system.cpu.iew.EXEC:nop 12876339 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.081001 # Inst execution rate
system.cpu.iew.EXEC:refs 219209030 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 66375463 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 788336695 # num instructions consuming a value
system.cpu.iew.WB:count 685357565 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.485374 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 382637953 # num instructions producing a value
system.cpu.iew.WB:rate 1.025304 # insts written-back per cycle
system.cpu.iew.WB:sent 714473572 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 25616212 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 2985344 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 194483391 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 2822926 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 7041770 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 112758143 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 971912060 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 152833567 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 22948891 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 722588050 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 111523 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 15327 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 58620851 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 199342 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 77 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 5719789 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 15891 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 94425 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 23277 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 67710242 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 55154074 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 94425 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 10897628 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 14718584 # Number of branches that were predicted taken incorrectly
system.cpu.int_regfile_reads 1644594876 # number of integer regfile reads
system.cpu.int_regfile_writes 527674952 # number of integer regfile writes
system.cpu.ipc 0.857727 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.857727 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 513661883 68.90% 68.90% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 386634 0.05% 68.95% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 68.95% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 106 0.00% 68.95% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 68.95% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 68.95% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 68.95% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 68.95% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 68.95% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 68.95% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 68.95% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 68.95% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 68.95% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 68.95% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 68.95% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 68.95% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 68.95% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 68.95% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 68.95% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 68.95% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 68.95% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 68.95% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 68.95% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 68.95% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 68.95% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 3 0.00% 68.95% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 68.95% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 68.95% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 68.95% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 160948708 21.59% 90.54% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 70539607 9.46% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total 745536941 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 10587544 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.014201 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 2110928 19.94% 19.94% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 19.94% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 19.94% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 19.94% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 19.94% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 19.94% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 19.94% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 19.94% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 19.94% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 19.94% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 19.94% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 19.94% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 19.94% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 19.94% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 19.94% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 19.94% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 19.94% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 19.94% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 19.94% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 19.94% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 19.94% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 19.94% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 19.94% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 19.94% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 19.94% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 19.94% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 19.94% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 19.94% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 19.94% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 5343659 50.47% 70.41% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 3132957 29.59% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples 663809705 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.123118 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.406431 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 308965401 46.54% 46.54% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 144668555 21.79% 68.34% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 110038020 16.58% 84.91% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 52350888 7.89% 92.80% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 29088648 4.38% 97.18% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 8324547 1.25% 98.44% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 7676240 1.16% 99.59% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 1874333 0.28% 99.88% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 823073 0.12% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 663809705 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.115333 # Inst issue rate
system.cpu.iq.fp_alu_accesses 126 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 248 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 340 # Number of floating instruction queue writes
system.cpu.iq.int_alu_accesses 756124359 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 2167725865 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 685357549 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes 1330295825 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 954351941 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 745536941 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 4683780 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 371189493 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 2254982 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 805916 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 656102390 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 344509 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34257.550447 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31005.397937 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 231966 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 3855447500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.326677 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 112543 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 3489440500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.326677 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 112543 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 863665 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34190.772563 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31027.525161 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 739947 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 4230014000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.143248 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 123718 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_hits 13 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_miss_latency 3838260000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.143233 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 123705 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 16 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_hits 13 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_miss_rate 0.187500 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 3 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 93000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.187500 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 3 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 1064084 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 1064084 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 6.437044 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 1208174 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34222.582229 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31016.984271 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 971913 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 8085461500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.195552 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 236261 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 13 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 7327700500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.195541 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 236248 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.213211 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.422279 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 6986.504420 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 13837.237986 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 1208174 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34222.582229 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31016.984271 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 971913 # number of overall hits
system.cpu.l2cache.overall_miss_latency 8085461500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.195552 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 236261 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 13 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 7327700500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.195541 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 236248 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 217136 # number of replacements
system.cpu.l2cache.sampled_refs 237363 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 20823.742406 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1527916 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 241420822000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 171788 # number of writebacks
system.cpu.memDep0.conflictingLoads 54696737 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 61739671 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 194483391 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 112758143 # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads 1214411471 # number of misc regfile reads
system.cpu.misc_regfile_writes 344749 # number of misc regfile writes
system.cpu.numCycles 668443504 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 12415646 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 448650778 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 9472750 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 295422634 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 10451000 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 22 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 2625367121 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 1059917765 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 772660527 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 221340746 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 58620851 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 26319878 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 324009746 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 1198 # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups 2625365923 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 49689950 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 2845114 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 73898765 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 2845067 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 1570084762 # The number of ROB reads
system.cpu.rob.rob_writes 2002485622 # The number of ROB writes
system.cpu.timesIdled 109548 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 548 # Number of system calls
---------- End Simulation Statistics ----------
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