blob: ce0258252b960b1244aae5b35208c7f666cf8fe9 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
|
---------- Begin Simulation Statistics ----------
sim_seconds 0.279789 # Number of seconds simulated
sim_ticks 279789017500 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 82238 # Simulator instruction rate (inst/s)
host_tick_rate 40132128 # Simulator tick rate (ticks/s)
host_mem_usage 268396 # Number of bytes of host memory used
host_seconds 6971.70 # Real time elapsed on the host
sim_insts 573340737 # Number of instructions simulated
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 548 # Number of system calls
system.cpu.numCycles 559578036 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 229313741 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 182941703 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 18381450 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 193404656 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 160578997 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 11881056 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 2583910 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 158920845 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 1008979483 # Number of instructions fetch has processed
system.cpu.fetch.Branches 229313741 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 172460053 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 261292498 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 78073694 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 78434846 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 86 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 74310 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 146143180 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 4810109 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 555823153 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.154722 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.836930 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 294542931 52.99% 52.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 24434943 4.40% 57.39% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 41500058 7.47% 64.85% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 40458286 7.28% 72.13% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 42543437 7.65% 79.79% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 15388331 2.77% 82.56% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 18846128 3.39% 85.95% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 16230001 2.92% 88.87% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 61879038 11.13% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 555823153 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.409798 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.803108 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 176155270 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 73642136 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 243542004 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 5471546 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 57012197 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 33378674 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 103333 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 1139235628 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 221531 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 57012197 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 192762447 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 6395244 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 52127193 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 232252715 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 15273357 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 1073234487 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 1226 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 2982497 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 8850274 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 56 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 1193556306 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 4743331903 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 4743328950 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 2953 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 672198616 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 521357685 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 2768330 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 2768349 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 48304499 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 196270626 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 121806649 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 17302899 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 13929275 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 937590667 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 4537458 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 765577672 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 3452362 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 365845767 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 1020513301 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 659897 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 555823153 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.377376 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.646867 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 247650578 44.56% 44.56% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 96155335 17.30% 61.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 83204777 14.97% 76.82% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 61794788 11.12% 87.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 37799799 6.80% 94.74% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 16279306 2.93% 97.67% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 7068984 1.27% 98.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 4337899 0.78% 99.72% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 1531687 0.28% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 555823153 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 140807 1.12% 1.12% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 1.12% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 1.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 1.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 1.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 1.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.12% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 6799143 54.23% 55.35% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 5597920 44.65% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 513475935 67.07% 67.07% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 381036 0.05% 67.12% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 132 0.00% 67.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.12% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 171848719 22.45% 89.57% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 79871847 10.43% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 765577672 # Type of FU issued
system.cpu.iq.rate 1.368134 # Inst issue rate
system.cpu.iq.fu_busy_cnt 12537870 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.016377 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 2102968429 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 1308573624 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 707132694 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 300 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 418 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 778115390 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 152 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 8455252 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 69497780 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 53390 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 614044 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 64202883 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 28348 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 333 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 57012197 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 2686334 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 121984 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 951489929 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 12656652 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 196270626 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 121806649 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 2752356 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 48623 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 7315 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 614044 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 18618092 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 6141777 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 24759869 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 733934042 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 162731362 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 31643630 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 9361804 # number of nop insts executed
system.cpu.iew.exec_refs 234660567 # number of memory reference insts executed
system.cpu.iew.exec_branches 147664615 # Number of branches executed
system.cpu.iew.exec_stores 71929205 # Number of stores executed
system.cpu.iew.exec_rate 1.311585 # Inst execution rate
system.cpu.iew.wb_sent 721950956 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 707132710 # cumulative count of insts written-back
system.cpu.iew.wb_producers 399859111 # num instructions producing a value
system.cpu.iew.wb_consumers 707515910 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.263689 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.565159 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 574684621 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 376818510 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 3877561 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 20574438 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 498810957 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.152109 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.870885 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 264965751 53.12% 53.12% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 115315817 23.12% 76.24% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 44565199 8.93% 85.17% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 20246779 4.06% 89.23% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 19896261 3.99% 93.22% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 7328254 1.47% 94.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 7611881 1.53% 96.21% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 3447651 0.69% 96.91% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 15433364 3.09% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 498810957 # Number of insts commited each cycle
system.cpu.commit.count 574684621 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 184376611 # Number of memory references committed
system.cpu.commit.loads 126772845 # Number of loads committed
system.cpu.commit.membars 1488542 # Number of memory barriers committed
system.cpu.commit.branches 120192030 # Number of branches committed
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
system.cpu.commit.int_insts 473700857 # Number of committed integer instructions.
system.cpu.commit.function_calls 9757362 # Number of function calls committed.
system.cpu.commit.bw_lim_events 15433364 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 1434873586 # The number of ROB reads
system.cpu.rob.rob_writes 1960359919 # The number of ROB writes
system.cpu.timesIdled 94610 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 3754883 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 573340737 # Number of Instructions Simulated
system.cpu.committedInsts_total 573340737 # Number of Instructions Simulated
system.cpu.cpi 0.975996 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.975996 # CPI: Total CPI of All Threads
system.cpu.ipc 1.024595 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.024595 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 3384956860 # number of integer regfile reads
system.cpu.int_regfile_writes 820192225 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
system.cpu.misc_regfile_reads 1253867001 # number of misc regfile reads
system.cpu.misc_regfile_writes 4463662 # number of misc regfile writes
system.cpu.icache.replacements 12859 # number of replacements
system.cpu.icache.tagsinuse 1069.062929 # Cycle average of tags in use
system.cpu.icache.total_refs 146126711 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 14705 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 9937.212581 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 1069.062929 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.522003 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 146126714 # number of ReadReq hits
system.cpu.icache.demand_hits 146126714 # number of demand (read+write) hits
system.cpu.icache.overall_hits 146126714 # number of overall hits
system.cpu.icache.ReadReq_misses 16466 # number of ReadReq misses
system.cpu.icache.demand_misses 16466 # number of demand (read+write) misses
system.cpu.icache.overall_misses 16466 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 235996000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 235996000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 235996000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 146143180 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 146143180 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 146143180 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000113 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000113 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000113 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 14332.321147 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 14332.321147 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 14332.321147 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 1664 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 1664 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 1664 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 14802 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 14802 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 14802 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 154077500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 154077500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 154077500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000101 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000101 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000101 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 10409.235238 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 10409.235238 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 10409.235238 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1212005 # number of replacements
system.cpu.dcache.tagsinuse 4056.899454 # Cycle average of tags in use
system.cpu.dcache.total_refs 205223733 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1216101 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 168.755501 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 5990497000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4056.899454 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.990454 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 147671766 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 52787083 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 2532910 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits 2231830 # number of StoreCondReq hits
system.cpu.dcache.demand_hits 200458849 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 200458849 # number of overall hits
system.cpu.dcache.ReadReq_misses 1234695 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 1452223 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses 55 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses 2686918 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 2686918 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 14259178500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 25049559493 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency 501000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency 39308737993 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 39308737993 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 148906461 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 54239306 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses 2532965 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses 2231830 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 203145767 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 203145767 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.008292 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.026774 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate 0.000022 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate 0.013227 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.013227 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 11548.745642 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 17249.113596 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency 9109.090909 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency 14629.675335 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 14629.675335 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 493000 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 60 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 8216.666667 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 1079434 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 358298 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 1112430 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits 55 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits 1470728 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 1470728 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 876397 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 339793 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 1216190 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 1216190 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 6322149500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 4329896000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 10652045500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 10652045500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.005886 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006265 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.005987 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.005987 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7213.796373 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12742.746319 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 8758.537317 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 8758.537317 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 218713 # number of replacements
system.cpu.l2cache.tagsinuse 21078.689035 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1567898 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 239082 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 6.557993 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 207809197000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 7685.698304 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 13392.990732 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.234549 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.408722 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 760512 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 1079434 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits 60 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits 232403 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 992915 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 992915 # number of overall hits
system.cpu.l2cache.ReadReq_misses 130232 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses 28 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses 107668 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 237900 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 237900 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 4454609000 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency 68500 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 3687681000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 8142290000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 8142290000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 890744 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 1079434 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses 88 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 340071 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 1230815 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 1230815 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.146206 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate 0.318182 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.316604 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.193287 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.193287 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34205.179986 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency 2446.428571 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34250.482966 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34225.683060 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34225.683060 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks 171082 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits 22 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits 22 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 22 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 130210 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses 28 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 107668 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 237878 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 237878 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 4042910500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 868000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 3338293500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 7381204000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 7381204000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.146181 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.318182 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.316604 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.193269 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.193269 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31049.155211 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31005.438013 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31029.367995 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31029.367995 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
|