blob: 24713e5f3eb6724e5729721b88d167e06c505862 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
|
---------- Begin Simulation Statistics ----------
host_inst_rate 1125820 # Simulator instruction rate (inst/s)
host_mem_usage 214880 # Number of bytes of host memory used
host_seconds 496.95 # Real time elapsed on the host
host_tick_rate 1500512692 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 559470527 # Number of instructions simulated
sim_seconds 0.745673 # Number of seconds simulated
sim_ticks 745672616000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 127326326 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 20914.908888 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17914.908888 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 126543330 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 16376290000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.006150 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 782996 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 14027302000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.006150 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 782996 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 55727847 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 53833.507889 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 50833.507889 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 55072849 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 35260840000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.011754 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 654998 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 33295846000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.011754 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 654998 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 159.673059 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 183054173 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 35909.141485 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 32909.141485 # average overall mshr miss latency
system.cpu.dcache.demand_hits 181616179 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 51637130000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.007856 # miss rate for demand accesses
system.cpu.dcache.demand_misses 1437994 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 47323148000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.007856 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 1437994 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.992972 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4067.215006 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 183054173 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 35909.141485 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 32909.141485 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 181616179 # number of overall hits
system.cpu.dcache.overall_miss_latency 51637130000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.007856 # miss rate for overall accesses
system.cpu.dcache.overall_misses 1437994 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 47323148000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.007856 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 1437994 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 1135200 # number of replacements
system.cpu.dcache.sampled_refs 1139296 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4067.215006 # Cycle average of tags in use
system.cpu.dcache.total_refs 181914877 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 11578483000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 808512 # number of writebacks
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.icache.ReadReq_accesses 512145761 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 24743.338252 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 21743.338252 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 512134240 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 285068000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000022 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 11521 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 250505000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 11521 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 44452.238521 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 512145761 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 24743.338252 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 21743.338252 # average overall mshr miss latency
system.cpu.icache.demand_hits 512134240 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 285068000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000022 # miss rate for demand accesses
system.cpu.icache.demand_misses 11521 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 250505000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000022 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 11521 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.485313 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 993.921198 # Average occupied blocks per context
system.cpu.icache.overall_accesses 512145761 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 24743.338252 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 21743.338252 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 512134240 # number of overall hits
system.cpu.icache.overall_miss_latency 285068000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000022 # miss rate for overall accesses
system.cpu.icache.overall_misses 11521 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 250505000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000022 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 11521 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 9788 # number of replacements
system.cpu.icache.sampled_refs 11521 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 993.921198 # Cycle average of tags in use
system.cpu.icache.total_refs 512134240 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 356300 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 33786 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 16770728000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.905175 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 322514 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 12900560000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.905175 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 322514 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 794517 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 662657 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 6856720000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.165962 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 131860 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 5274400000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165962 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 131860 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 298698 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51993.732800 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 15530424000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 298698 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 11947920000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 298698 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 808512 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 808512 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 4.737661 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 1150817 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 696443 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 23627448000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.394827 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 454374 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 18174960000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.394827 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 454374 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.184240 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.380639 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 6037.178832 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 12472.788257 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 1150817 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 696443 # number of overall hits
system.cpu.l2cache.overall_miss_latency 23627448000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.394827 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 454374 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 18174960000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.394827 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 454374 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 232496 # number of replacements
system.cpu.l2cache.sampled_refs 251560 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 18509.967089 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1191806 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 525324932000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 186433 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 1491345232 # number of cpu cycles simulated
system.cpu.num_insts 559470527 # Number of instructions executed
system.cpu.num_refs 184987503 # Number of memory references
system.cpu.workload.PROG:num_syscalls 548 # Number of system calls
---------- End Simulation Statistics ----------
|