blob: f9d747bd5cd3e7aad35d8aecaa25803956ab5584 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
|
---------- Begin Simulation Statistics ----------
sim_seconds 0.722234 # Number of seconds simulated
sim_ticks 722234364000 # Number of ticks simulated
final_tick 722234364000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1518630 # Simulator instruction rate (inst/s)
host_tick_rate 1927485562 # Simulator tick rate (ticks/s)
host_mem_usage 222536 # Number of bytes of host memory used
host_seconds 374.70 # Real time elapsed on the host
sim_insts 569034848 # Number of instructions simulated
system.physmem.bytes_read 14797056 # Number of bytes read from this memory
system.physmem.bytes_inst_read 188608 # Number of instructions bytes read from this memory
system.physmem.bytes_written 11027328 # Number of bytes written to this memory
system.physmem.num_reads 231204 # Number of read requests responded to by this memory
system.physmem.num_writes 172302 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 20487887 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 261145 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 15268351 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 35756238 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 548 # Number of system calls
system.cpu.numCycles 1444468728 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.num_insts 569034848 # Number of instructions executed
system.cpu.num_int_alu_accesses 470727703 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
system.cpu.num_func_calls 15725605 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 95872736 # number of instructions that are conditional controls
system.cpu.num_int_insts 470727703 # number of integer instructions
system.cpu.num_fp_insts 16 # number of float instructions
system.cpu.num_int_register_reads 2844375220 # number of times the integer registers were read
system.cpu.num_int_register_writes 646169365 # number of times the integer registers were written
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 182890035 # number of memory refs
system.cpu.num_load_insts 126029556 # Number of load instructions
system.cpu.num_store_insts 56860479 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 1444468728 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 9788 # number of replacements
system.cpu.icache.tagsinuse 984.426148 # Cycle average of tags in use
system.cpu.icache.total_refs 516599864 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 11521 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 44839.845847 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 984.426148 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.480677 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 516599864 # number of ReadReq hits
system.cpu.icache.demand_hits 516599864 # number of demand (read+write) hits
system.cpu.icache.overall_hits 516599864 # number of overall hits
system.cpu.icache.ReadReq_misses 11521 # number of ReadReq misses
system.cpu.icache.demand_misses 11521 # number of demand (read+write) misses
system.cpu.icache.overall_misses 11521 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 285068000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 285068000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 285068000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 516611385 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 516611385 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 516611385 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000022 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000022 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000022 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 24743.338252 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 24743.338252 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 24743.338252 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 11521 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 11521 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 11521 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 250505000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 250505000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 250505000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000022 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000022 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 21743.338252 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 21743.338252 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 21743.338252 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1134822 # number of replacements
system.cpu.dcache.tagsinuse 4065.490059 # Cycle average of tags in use
system.cpu.dcache.total_refs 179817787 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1138918 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 157.884753 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 11889987000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4065.490059 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.992551 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 122957659 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 53883046 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 1488541 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits 1488541 # number of StoreCondReq hits
system.cpu.dcache.demand_hits 176840705 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 176840705 # number of overall hits
system.cpu.dcache.ReadReq_misses 782658 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 356260 # number of WriteReq misses
system.cpu.dcache.demand_misses 1138918 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 1138918 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 15502704000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 10028942000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency 25531646000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 25531646000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 123740317 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 54239306 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses 1488541 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses 1488541 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 177979623 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 177979623 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.006325 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.006568 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate 0.006399 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.006399 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 19807.762778 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 28150.625947 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency 22417.457622 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 22417.457622 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 1025440 # number of writebacks
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 782658 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 356260 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 1138918 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 1138918 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 13154730000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 8960162000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 22114892000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 22114892000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.006325 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006568 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.006399 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.006399 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 16807.762778 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 25150.625947 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 19417.457622 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 19417.457622 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 212089 # number of replacements
system.cpu.l2cache.tagsinuse 20443.163614 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1426644 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 232128 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 6.145937 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 513135223000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 5849.157602 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 14594.006011 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.178502 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.445374 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 683006 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 1025440 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 236229 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 919235 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 919235 # number of overall hits
system.cpu.l2cache.ReadReq_misses 111173 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 120031 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 231204 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 231204 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 5780996000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 6241612000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 12022608000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 12022608000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 794179 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 1025440 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 356260 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 1150439 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 1150439 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.139985 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.336920 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.200970 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.200970 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks 172302 # number of writebacks
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 111173 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 120031 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 231204 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 231204 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 4446920000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 4801240000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 9248160000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 9248160000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.139985 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.336920 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.200970 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.200970 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
|
